[v2,04/15] drm/i915/dsb: Added enum for reg write capability.
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Message ID 20190821063236.19705-5-animesh.manna@intel.com
State New
Headers show
Series
  • DSB enablement.
Related show

Commit Message

Animesh Manna Aug. 21, 2019, 6:32 a.m. UTC
DSB can access specific register, To identify those register
which can be written through DSB, enum reg_write_cap is added
to hold the capability.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Jani Nikula Aug. 22, 2019, 12:57 p.m. UTC | #1
On Wed, 21 Aug 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> DSB can access specific register, To identify those register
> which can be written through DSB, enum reg_write_cap is added
> to hold the capability.

This patch alone increases i915.ko size by about 200k.

Obviously, no.

We've considered making reg a bitfield with 31 bits for offset and 1 bit
to denote display uncore. Might be worthwhile. But I don't think this is
the way to go here.

BR,
Jani.

>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2abd199093c5..c4a17034d4dc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -178,11 +178,22 @@
>   */
>  #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
>  
> +/*
> + * Added enum to hold the capability for those registers which can be written
> + * through DSB.
> + */
> +enum reg_write_cap {
> +	MMIO_WRITE,
> +	DSB_WRITE,
> +	DSB_INDEX_WRITE
> +};
> +
>  typedef struct {
>  	u32 reg;
> +	enum reg_write_cap cap;
>  } i915_reg_t;
>  
> -#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
> +#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__})
>  
>  #define INVALID_MMIO_REG _MMIO(0)

Patch
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2abd199093c5..c4a17034d4dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,11 +178,22 @@ 
  */
 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
 
+/*
+ * Added enum to hold the capability for those registers which can be written
+ * through DSB.
+ */
+enum reg_write_cap {
+	MMIO_WRITE,
+	DSB_WRITE,
+	DSB_INDEX_WRITE
+};
+
 typedef struct {
 	u32 reg;
+	enum reg_write_cap cap;
 } i915_reg_t;
 
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__})
 
 #define INVALID_MMIO_REG _MMIO(0)