[07/11] drm/i915: Use subslice stride to set subslices for a given slice
diff mbox series

Message ID 20190822183213.132380-8-stuart.summers@intel.com
State New
Headers show
Series
  • Refactor to expand subslice mask (rev 2)
Related show

Commit Message

Summers, Stuart Aug. 22, 2019, 6:32 p.m. UTC
Add a subslice stride calculation when setting subslices. This
aligns more closely with the userspace expectation of the subslice
mask structure.

v2: Use local variable for subslice_mask on HSW and
    clean up a few other subslice_mask local variable
    changes
v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
    Split main set function and refactors in intel_device_info.c
    into separate patches (Chris)
v4: Reduce ss_stride size check when setting subslices per slice
    based on actual expected max stride (Chris)
    Move that GEM_BUG_ON check for the ss_stride out to the patch
    which adds the ss_stride

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++--
 drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

Comments

Chris Wilson Aug. 22, 2019, 10:43 p.m. UTC | #1
Quoting Stuart Summers (2019-08-22 19:32:09)
> Add a subslice stride calculation when setting subslices. This
> aligns more closely with the userspace expectation of the subslice
> mask structure.
> 
> v2: Use local variable for subslice_mask on HSW and
>     clean up a few other subslice_mask local variable
>     changes
> v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
>     Split main set function and refactors in intel_device_info.c
>     into separate patches (Chris)
> v4: Reduce ss_stride size check when setting subslices per slice
>     based on actual expected max stride (Chris)
>     Move that GEM_BUG_ON check for the ss_stride out to the patch
>     which adds the ss_stride
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++--
>  drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 3a5db0dbac72..a0d32270248c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -33,9 +33,13 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
>  }
>  
>  void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> -                             u8 ss_mask)
> +                             u32 ss_mask)
>  {
> -       sseu->subslice_mask[slice] = ss_mask;
> +       int i, offset = slice * sseu->ss_stride;
> +
> +       for (i = 0; i < sseu->ss_stride; i++)
> +               sseu->subslice_mask[offset + i] =
> +                       (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;

Is it not

	memcpy(&sseu->sublice_mask[offset], &ss_mask, sseu->ss_stride);
?
-Chris
Summers, Stuart Aug. 23, 2019, 3:59 p.m. UTC | #2
On Thu, 2019-08-22 at 23:43 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-22 19:32:09)
> > Add a subslice stride calculation when setting subslices. This
> > aligns more closely with the userspace expectation of the subslice
> > mask structure.
> > 
> > v2: Use local variable for subslice_mask on HSW and
> >     clean up a few other subslice_mask local variable
> >     changes
> > v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
> >     Split main set function and refactors in intel_device_info.c
> >     into separate patches (Chris)
> > v4: Reduce ss_stride size check when setting subslices per slice
> >     based on actual expected max stride (Chris)
> >     Move that GEM_BUG_ON check for the ss_stride out to the patch
> >     which adds the ss_stride
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++--
> >  drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> >  2 files changed, 7 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 3a5db0dbac72..a0d32270248c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -33,9 +33,13 @@ intel_sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> >  }
> >  
> >  void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int
> > slice,
> > -                             u8 ss_mask)
> > +                             u32 ss_mask)
> >  {
> > -       sseu->subslice_mask[slice] = ss_mask;
> > +       int i, offset = slice * sseu->ss_stride;
> > +
> > +       for (i = 0; i < sseu->ss_stride; i++)
> > +               sseu->subslice_mask[offset + i] =
> > +                       (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
> 
> Is it not
> 
> 	memcpy(&sseu->sublice_mask[offset], &ss_mask, sseu->ss_stride);

True.. update coming shortly.

Thanks,
Stuart

> ?
> -Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 3a5db0dbac72..a0d32270248c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -33,9 +33,13 @@  intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
 }
 
 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
-			      u8 ss_mask)
+			      u32 ss_mask)
 {
-	sseu->subslice_mask[slice] = ss_mask;
+	int i, offset = slice * sseu->ss_stride;
+
+	for (i = 0; i < sseu->ss_stride; i++)
+		sseu->subslice_mask[offset + i] =
+			(ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
 }
 
 unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 7f600f50dedb..73a9064291a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -79,7 +79,7 @@  unsigned int
 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
 
 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
-			      u8 ss_mask);
+			      u32 ss_mask);
 
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 			 const struct intel_sseu *req_sseu);