diff mbox series

drm/i915/tgl: Enabling DSC on Pipe A for TGL

Message ID 20190823004655.28905-1-madhumitha.tolakanahalli.pradeep@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/tgl: Enabling DSC on Pipe A for TGL | expand

Commit Message

Tolakanahalli Pradeep, Madhumitha Aug. 23, 2019, 12:46 a.m. UTC
DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
all the pipes support DSC. Hence, the DSC and FEC restriction on
Pipe A needs to be removed.

v2: Changes in the logic around removing the restriction around
    Pipe A (Manasi, Lucas)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

Comments

Navare, Manasi Aug. 23, 2019, 12:59 a.m. UTC | #1
On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep wrote:
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
> 
> v2: Changes in the logic around removing the restriction around
>     Pipe A (Manasi, Lucas)
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>

Looks good to me

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..e2c8fe274c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	return INTEL_GEN(dev_priv) >= 11 &&
> -		pipe_config->cpu_transcoder != TRANSCODER_A;
> +	/* On TGL, FEC is supported on all Pipes */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return true;
> +
> +	if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> +		return true;
> +
> +	return false;
>  }
>  
>  static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	return INTEL_GEN(dev_priv) >= 10 &&
> -		pipe_config->cpu_transcoder != TRANSCODER_A;
> +	/* On TGL, DSC is supported on all Pipes */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return true;
> +
> +	if (INTEL_GEN(dev_priv) >= 10 &&
> +	    pipe_config->cpu_transcoder != TRANSCODER_A)
> +		return true;
> +
> +	return false;
>  }
>  
>  static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> -- 
> 2.17.1
>
Lucas De Marchi Aug. 23, 2019, 8:50 a.m. UTC | #2
On Thu, Aug 22, 2019 at 5:46 PM Madhumitha Tolakanahalli Pradeep
<madhumitha.tolakanahalli.pradeep@intel.com> wrote:
>
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
>
> v2: Changes in the logic around removing the restriction around
>     Pipe A (Manasi, Lucas)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..e2c8fe274c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>  {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> -       return INTEL_GEN(dev_priv) >= 11 &&
> -               pipe_config->cpu_transcoder != TRANSCODER_A;
> +       /* On TGL, FEC is supported on all Pipes */
> +       if (INTEL_GEN(dev_priv) >= 12)
> +               return true;
> +
> +       if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> +               return true;
> +
> +       return false;
>  }
>
>  static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> -       return INTEL_GEN(dev_priv) >= 10 &&
> -               pipe_config->cpu_transcoder != TRANSCODER_A;
> +       /* On TGL, DSC is supported on all Pipes */
> +       if (INTEL_GEN(dev_priv) >= 12)
> +               return true;
> +
> +       if (INTEL_GEN(dev_priv) >= 10 &&
> +           pipe_config->cpu_transcoder != TRANSCODER_A)
> +               return true;
> +
> +       return false;
>  }
>
>  static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Navare, Manasi Aug. 28, 2019, 8:12 p.m. UTC | #3
Thanks for the patch and reviews, pushed to dinq

Regards
Manasi

On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep wrote:
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
> 
> v2: Changes in the logic around removing the restriction around
>     Pipe A (Manasi, Lucas)
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..e2c8fe274c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	return INTEL_GEN(dev_priv) >= 11 &&
> -		pipe_config->cpu_transcoder != TRANSCODER_A;
> +	/* On TGL, FEC is supported on all Pipes */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return true;
> +
> +	if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> +		return true;
> +
> +	return false;
>  }
>  
>  static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	return INTEL_GEN(dev_priv) >= 10 &&
> -		pipe_config->cpu_transcoder != TRANSCODER_A;
> +	/* On TGL, DSC is supported on all Pipes */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return true;
> +
> +	if (INTEL_GEN(dev_priv) >= 10 &&
> +	    pipe_config->cpu_transcoder != TRANSCODER_A)
> +		return true;
> +
> +	return false;
>  }
>  
>  static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> -- 
> 2.17.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..e2c8fe274c84 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1739,8 +1739,14 @@  static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	return INTEL_GEN(dev_priv) >= 11 &&
-		pipe_config->cpu_transcoder != TRANSCODER_A;
+	/* On TGL, FEC is supported on all Pipes */
+	if (INTEL_GEN(dev_priv) >= 12)
+		return true;
+
+	if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
+		return true;
+
+	return false;
 }
 
 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
@@ -1755,8 +1761,15 @@  static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	return INTEL_GEN(dev_priv) >= 10 &&
-		pipe_config->cpu_transcoder != TRANSCODER_A;
+	/* On TGL, DSC is supported on all Pipes */
+	if (INTEL_GEN(dev_priv) >= 12)
+		return true;
+
+	if (INTEL_GEN(dev_priv) >= 10 &&
+	    pipe_config->cpu_transcoder != TRANSCODER_A)
+		return true;
+
+	return false;
 }
 
 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,