drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+
diff mbox series

Message ID 20190822163133.27587-1-matthew.d.roper@intel.com
State New
Headers show
Series
  • drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+
Related show

Commit Message

Matt Roper Aug. 22, 2019, 4:31 p.m. UTC
The bspec was recently updated with these new cdclk values for ICL, EHL,
and TGL.

Bspec: 20598
Bspec: 49201
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

Comments

Souza, Jose Aug. 23, 2019, 5:47 p.m. UTC | #1
On Thu, 2019-08-22 at 09:31 -0700, Matt Roper wrote:
> The bspec was recently updated with these new cdclk values for ICL,
> EHL,
> and TGL.
> 
> Bspec: 20598
> Bspec: 49201

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d0bc42e5039c..0be137a9129a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1748,8 +1748,10 @@ static void cnl_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
>  
>  static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
>  {
> -	static const int ranges_24[] = { 180000, 192000, 312000,
> 552000, 648000 };
> -	static const int ranges_19_38[] = { 172800, 192000, 307200,
> 556800, 652800 };
> +	static const int ranges_24[] = { 180000, 192000, 312000,
> 324000,
> +					 552000, 648000 };
> +	static const int ranges_19_38[] = { 172800, 192000, 307200,
> 326400,
> +					    556800, 652800 };
>  	const int *ranges;
>  	int len, i;
>  
> @@ -1790,6 +1792,7 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
>  		/* fall through */
>  	case 172800:
>  	case 307200:
> +	case 326400:
>  	case 556800:
>  	case 652800:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> @@ -1797,6 +1800,7 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
>  		break;
>  	case 180000:
>  	case 312000:
> +	case 324000:
>  	case 552000:
>  	case 648000:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
Matt Roper Aug. 23, 2019, 10:17 p.m. UTC | #2
On Thu, Aug 22, 2019 at 09:31:33AM -0700, Matt Roper wrote:
> The bspec was recently updated with these new cdclk values for ICL, EHL,
> and TGL.
> 
> Bspec: 20598
> Bspec: 49201
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Looking more closely, I think we actually need a bit more than just this
patch.  These new values are the only ones that use a /2 CD2X divider
rather than a /1 divider.  So we also need to program the divider
properly as well (currently the ICL code assumes it will always be /1).


Matt

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d0bc42e5039c..0be137a9129a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1748,8 +1748,10 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  
>  static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
>  {
> -	static const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 };
> -	static const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
> +	static const int ranges_24[] = { 180000, 192000, 312000, 324000,
> +					 552000, 648000 };
> +	static const int ranges_19_38[] = { 172800, 192000, 307200, 326400,
> +					    556800, 652800 };
>  	const int *ranges;
>  	int len, i;
>  
> @@ -1790,6 +1792,7 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  		/* fall through */
>  	case 172800:
>  	case 307200:
> +	case 326400:
>  	case 556800:
>  	case 652800:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> @@ -1797,6 +1800,7 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  		break;
>  	case 180000:
>  	case 312000:
> +	case 324000:
>  	case 552000:
>  	case 648000:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> -- 
> 2.20.1
>

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d0bc42e5039c..0be137a9129a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1748,8 +1748,10 @@  static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 
 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
 {
-	static const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 };
-	static const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
+	static const int ranges_24[] = { 180000, 192000, 312000, 324000,
+					 552000, 648000 };
+	static const int ranges_19_38[] = { 172800, 192000, 307200, 326400,
+					    556800, 652800 };
 	const int *ranges;
 	int len, i;
 
@@ -1790,6 +1792,7 @@  static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 		/* fall through */
 	case 172800:
 	case 307200:
+	case 326400:
 	case 556800:
 	case 652800:
 		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
@@ -1797,6 +1800,7 @@  static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 		break;
 	case 180000:
 	case 312000:
+	case 324000:
 	case 552000:
 	case 648000:
 		WARN_ON(dev_priv->cdclk.hw.ref != 24000);