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Fri, 23 Aug 2019 19:11:38 +0000 Received: from VI1PR0402MB2863.eurprd04.prod.outlook.com ([fe80::7de6:ea4b:9b5d:d023]) by VI1PR0402MB2863.eurprd04.prod.outlook.com ([fe80::7de6:ea4b:9b5d:d023%7]) with mapi id 15.20.2178.020; Fri, 23 Aug 2019 19:11:38 +0000 From: Stefan-gabriel Mirea To: "corbet@lwn.net" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "gregkh@linuxfoundation.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "shawnguo@kernel.org" , Leo Li Subject: [PATCH v3 5/7] arm64: dts: fsl: Add device tree for S32V234-EVB Thread-Topic: [PATCH v3 5/7] arm64: dts: fsl: Add device tree for S32V234-EVB Thread-Index: AQHVWeaWO37el/dGLkW2Jfweldu8gQ== Date: Fri, 23 Aug 2019 19:11:38 +0000 Message-ID: <20190823191115.18490-6-stefan-gabriel.mirea@nxp.com> References: <20190823191115.18490-1-stefan-gabriel.mirea@nxp.com> In-Reply-To: <20190823191115.18490-1-stefan-gabriel.mirea@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.22.0 x-clientproxiedby: AM5PR0402CA0007.eurprd04.prod.outlook.com (2603:10a6:203:90::17) To VI1PR0402MB2863.eurprd04.prod.outlook.com (2603:10a6:800:af::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=stefan-gabriel.mirea@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0402MB2717; H:VI1PR0402MB2863.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 5wNwbk9q7cxxlXCOoH6l7aqO4S+5PNaeO32Nl3aX63NvVV5ft8P5Xr8P/TY7QlYAxK0tOxlnVr9Mq1R5MgaVB440HlerwIteeK4oLI9xw8TkFsw70lrFLjd3SPOXeQVnT05sgVUvlnzt+/GRTMuBQBhCiX9wsaeru6YAoAAQ+BSqi5zb2FQOZbuczkHxVF57ZJxpVhhZqi5wstxroQgfaqS5hDXuFICBJZhg6jC9qzE/EnNEnIKo90c2bNdnP3hXR4iL8gbWaLxatZnxq8+MaLa9BIrYES3LJuSh1A0Pm9UC3CoW80O0iDxbCSl9/s2STSorTtkS3sC44IvnxzaF8lFKjLiXFm+72jpBJ4WOzdg1bMcaLmgXVZ6AeloS1Zc8wLBbq21dKkq3qktHYtCZAuYQFH5bKXOf/uFGnPOrW0E= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7e14f39a-7bb2-42f9-5260-08d727fdb94c X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Aug 2019 19:11:38.7679 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XAygUf2oy5PgaTGCgkD4WVHei9ODmCTceogWmCWXkdHzg4t1lNVbEo6lSh1UAWDoAr8D8ZsAMz6SYdGEpH+/hR+ujTJnuqYVqXS2eNq056Y= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB2717 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190823_121144_969702_FF78AE63 X-CRM114-Status: GOOD ( 14.56 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a01:111:f400:fe06:0:0:0:618 listed in] [list.dnswl.org] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , Larisa Ileana Grigore , "linux-kernel@vger.kernel.org" , Dan Nica , "linux-serial@vger.kernel.org" , "jslaby@suse.com" , Cosmin Stefan Stoica , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stoica Cosmin-Stefan Add initial version of device tree for S32V234-EVB, including nodes for the 4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and Generic Interrupt Controller (GIC). Keep SoC level separate from board level to let future boards with this SoC share common properties, while the dts files will keep board-dependent properties. Signed-off-by: Stoica Cosmin-Stefan Signed-off-by: Mihaela Martinas Signed-off-by: Dan Nica Signed-off-by: Larisa Grigore Signed-off-by: Phu Luu An Signed-off-by: Stefan-Gabriel Mirea --- arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/s32v234-evb.dts | 25 ++++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 139 ++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32v234-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/s32v234.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c043aca66572..9aff21324146 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -26,3 +26,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb + +dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boot/dts/freescale/s32v234-evb.dts new file mode 100644 index 000000000000..4b802518cefc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234-evb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + */ + +/dts-v1/; +#include "s32v234.dtsi" + +/ { + model = "NXP S32V234-EVB2 Board"; + compatible = "fsl,s32v234-evb", "fsl,s32v234"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi new file mode 100644 index 000000000000..37225191ccbf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + */ + +#include + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,s32v234"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster0_l2_cache>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster0_l2_cache>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster1_l2_cache>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster1_l2_cache>; + }; + + cluster0_l2_cache: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2_cache: l2-cache1 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + /* clock-frequency might be modified by u-boot, depending on the + * chip version. + */ + clock-frequency = <10000000>; + }; + + gic: interrupt-controller@7d001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x7d001000 0 0x1000>, + <0 0x7d002000 0 0x2000>, + <0 0x7d004000 0 0x2000>, + <0 0x7d006000 0 0x2000>; + interrupts = ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + aips0: aips-bus@40000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + reg = <0x0 0x40000000 0x0 0x7D000>; + ranges; + + uart0: serial@40053000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x0 0x40053000 0x0 0x1000>; + interrupts = ; + status = "disabled"; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + reg = <0x0 0x40080000 0x0 0x70000>; + ranges; + + uart1: serial@400bc000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x0 0x400bc000 0x0 0x1000>; + interrupts = ; + status = "disabled"; + }; + }; + }; +};