Message ID | 01efc597b0d12ec51e6bb829b4bfe0f6c4dca2a4.1566603412.git.alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add RISC-V Hypervisor Extension v0.4 | expand |
On Fri, 23 Aug 2019 16:38:13 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu_bits.h | 11 ++++ > target/riscv/csr.c | 119 ++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 130 insertions(+) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 204d9d9a79..78067901a2 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -191,6 +191,17 @@ > #define HGATP_PPN SATP64_PPN > #endif > > +/* Virtual CSRs */ > +#define CSR_VSSTATUS 0x200 > +#define CSR_VSIE 0x204 > +#define CSR_VSTVEC 0x205 > +#define CSR_VSSCRATCH 0x240 > +#define CSR_VSEPC 0x241 > +#define CSR_VSCAUSE 0x242 > +#define CSR_VSTVAL 0x243 > +#define CSR_VSIP 0x244 > +#define CSR_VSATP 0x280 > + > /* Physical Memory Protection */ > #define CSR_PMPCFG0 0x3a0 > #define CSR_PMPCFG1 0x3a1 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 388775d45a..e2e908fbc0 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -817,6 +817,115 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) > return 0; > } > > +/* Virtual CSR Registers */ > +static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vsstatus; > + return 0; > +} > + > +static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vsstatus = val; > + return 0; > +} > + > +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vsie; > + return 0; > +} > + > +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vsie = val; > + return 0; > +} > + > +static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vstvec; > + return 0; > +} > + > +static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vstvec = val; > + return 0; > +} > + > +static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vsscratch; > + return 0; > +} > + > +static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vsscratch = val; > + return 0; > +} > + > +static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vsepc; > + return 0; > +} > + > +static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vsepc = val; > + return 0; > +} > + > +static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vscause; > + return 0; > +} > + > +static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vscause = val; > + return 0; > +} > + > +static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vstval; > + return 0; > +} > + > +static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vstval = val; > + return 0; > +} > + > +static int read_vsip(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = (target_ulong)atomic_read(&env->vsip); > + return 0; > +} > + > +static int write_vsip(CPURISCVState *env, int csrno, target_ulong val) > +{ > + atomic_set(&env->vsip, val); > + return 0; > +} > + > +static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->vsatp; > + return 0; > +} > + > +static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->vsatp = val; > + return 0; > +} > + > /* Physical Memory Protection */ > static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) > { > @@ -1018,6 +1127,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, > [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, > > + [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, > + [CSR_VSIE] = { hmode, read_vsie, write_vsie }, > + [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, > + [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, > + [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, > + [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, > + [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, > + [CSR_VSIP] = { hmode, read_vsip, write_vsip }, > + [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, > + > /* Physical Memory Protection */ > [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 204d9d9a79..78067901a2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -191,6 +191,17 @@ #define HGATP_PPN SATP64_PPN #endif +/* Virtual CSRs */ +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 388775d45a..e2e908fbc0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -817,6 +817,115 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* Virtual CSR Registers */ +static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vsstatus; + return 0; +} + +static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsstatus = val; + return 0; +} + +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vsie; + return 0; +} + +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsie = val; + return 0; +} + +static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vstvec; + return 0; +} + +static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstvec = val; + return 0; +} + +static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vsscratch; + return 0; +} + +static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsscratch = val; + return 0; +} + +static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vsepc; + return 0; +} + +static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsepc = val; + return 0; +} + +static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vscause; + return 0; +} + +static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vscause = val; + return 0; +} + +static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vstval; + return 0; +} + +static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstval = val; + return 0; +} + +static int read_vsip(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = (target_ulong)atomic_read(&env->vsip); + return 0; +} + +static int write_vsip(CPURISCVState *env, int csrno, target_ulong val) +{ + atomic_set(&env->vsip, val); + return 0; +} + +static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->vsatp; + return 0; +} + +static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsatp = val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1018,6 +1127,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, + [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, + [CSR_VSIE] = { hmode, read_vsie, write_vsie }, + [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, + [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, + [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, + [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, + [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, + [CSR_VSIP] = { hmode, read_vsip, write_vsip }, + [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu_bits.h | 11 ++++ target/riscv/csr.c | 119 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+)