| Message ID | 1566800772-18412-8-git-send-email-swati2.sharma@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: adding state checker for gamma lut value | expand |
>-----Original Message----- >From: Sharma, Swati2 >Sent: Monday, August 26, 2019 11:56 AM >To: intel-gfx@lists.freedesktop.org >Cc: Nikula, Jani <jani.nikula@intel.com>; Sharma, Shashank ><shashank.sharma@intel.com>; Manna, Animesh <animesh.manna@intel.com>; >Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; daniel.vetter@ffwll.ch; >ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>; Sharma, >Swati2 <swati2.sharma@intel.com> >Subject: [v8][PATCH 07/10] drm/i915/display: Extract chv_read_luts() > >For cherryview, have hw read out to create hw blob of gamma lut values. Same comments as previous patch. >Signed-off-by: Swati Sharma <swati2.sharma@intel.com> >--- > drivers/gpu/drm/i915/display/intel_color.c | 39 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 2 files changed, 42 insertions(+) > >diff --git a/drivers/gpu/drm/i915/display/intel_color.c >b/drivers/gpu/drm/i915/display/intel_color.c >index c77bbed..1ec2fa0 100644 >--- a/drivers/gpu/drm/i915/display/intel_color.c >+++ b/drivers/gpu/drm/i915/display/intel_color.c >@@ -1609,6 +1609,44 @@ static void i965_read_luts(struct intel_crtc_state >*crtc_state) > crtc_state->base.gamma_lut = >i965_read_gamma_lut_10p6(crtc_state); > } > >+static struct drm_property_blob * >+chv_read_cgm_gamma_lut(struct intel_crtc_state *crtc_state) { Make it const. If planning to use same for degamma as well, drop gamma from function name to have it generic. >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >+ u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; >+ enum pipe pipe = crtc->pipe; >+ struct drm_property_blob *blob; >+ struct drm_color_lut *blob_data; >+ >+ blob = drm_property_create_blob(&dev_priv->drm, >+ sizeof(struct drm_color_lut) * lut_size, >+ NULL); >+ if (IS_ERR(blob)) >+ return NULL; >+ >+ blob_data = blob->data; >+ >+ for (i = 0; i < lut_size; i++) { >+ val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0)); >+ blob_data[i].green = >intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10); >+ blob_data[i].blue = >+intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10); Wrap these lines. >+ >+ val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1)); >+ blob_data[i].red = >intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10); >+ } >+ >+ return blob; >+} >+ >+static void chv_read_luts(struct intel_crtc_state *crtc_state) { >+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) >+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); >+ else >+ crtc_state->base.gamma_lut = >chv_read_cgm_gamma_lut(crtc_state); >+} >+ > void intel_color_init(struct intel_crtc *crtc) { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -1621,6 >+1659,7 @@ void intel_color_init(struct intel_crtc *crtc) > dev_priv->display.color_check = chv_color_check; > dev_priv->display.color_commit = i9xx_color_commit; > dev_priv->display.load_luts = chv_load_luts; >+ dev_priv->display.read_luts = chv_read_luts; > } else if (INTEL_GEN(dev_priv) >= 4) { > dev_priv->display.color_check = i9xx_color_check; > dev_priv->display.color_commit = i9xx_color_commit; diff -- >git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index >b30b0c6b..e76e779 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -10307,6 +10307,9 @@ enum skl_power_gate { > #define CGM_PIPE_MODE_GAMMA (1 << 2) > #define CGM_PIPE_MODE_CSC (1 << 1) > #define CGM_PIPE_MODE_DEGAMMA (1 << 0) >+#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) >+#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) >+#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) > > #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) > #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) >-- >1.9.1
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index c77bbed..1ec2fa0 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1609,6 +1609,44 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state) crtc_state->base.gamma_lut = i965_read_gamma_lut_10p6(crtc_state); } +static struct drm_property_blob * +chv_read_cgm_gamma_lut(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *blob_data; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + blob_data = blob->data; + + for (i = 0; i < lut_size; i++) { + val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0)); + blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10); + blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10); + + val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1)); + blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10); + } + + return blob; +} + +static void chv_read_luts(struct intel_crtc_state *crtc_state) +{ + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); + else + crtc_state->base.gamma_lut = chv_read_cgm_gamma_lut(crtc_state); +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -1621,6 +1659,7 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_check = chv_color_check; dev_priv->display.color_commit = i9xx_color_commit; dev_priv->display.load_luts = chv_load_luts; + dev_priv->display.read_luts = chv_read_luts; } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv->display.color_check = i9xx_color_check; dev_priv->display.color_commit = i9xx_color_commit; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b30b0c6b..e76e779 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10307,6 +10307,9 @@ enum skl_power_gate { #define CGM_PIPE_MODE_GAMMA (1 << 2) #define CGM_PIPE_MODE_CSC (1 << 1) #define CGM_PIPE_MODE_DEGAMMA (1 << 0) +#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) +#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) +#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
For cherryview, have hw read out to create hw blob of gamma lut values. Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 39 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 42 insertions(+)