| Message ID | 1566800772-18412-10-git-send-email-swati2.sharma@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: adding state checker for gamma lut value | expand |
>-----Original Message----- >From: Sharma, Swati2 >Sent: Monday, August 26, 2019 11:56 AM >To: intel-gfx@lists.freedesktop.org >Cc: Nikula, Jani <jani.nikula@intel.com>; Sharma, Shashank ><shashank.sharma@intel.com>; Manna, Animesh <animesh.manna@intel.com>; >Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; daniel.vetter@ffwll.ch; >ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>; Sharma, >Swati2 <swati2.sharma@intel.com> >Subject: [v8][PATCH 09/10] drm/i915/display: Extract glk_read_luts() > >For glk, have hw read out to create hw blob of gamma lut values. Same as earlier patches. >Signed-off-by: Swati Sharma <swati2.sharma@intel.com> >--- > drivers/gpu/drm/i915/display/intel_color.c | 48 ++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/i915_reg.h | 3 ++ > 2 files changed, 49 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_color.c >b/drivers/gpu/drm/i915/display/intel_color.c >index 4b9b28f..3762bdf 100644 >--- a/drivers/gpu/drm/i915/display/intel_color.c >+++ b/drivers/gpu/drm/i915/display/intel_color.c >@@ -1684,6 +1684,49 @@ static void ilk_read_luts(struct intel_crtc_state >*crtc_state) > crtc_state->base.gamma_lut = ilk_read_gamma_lut(crtc_state); } > >+static struct drm_property_blob * >+glk_read_lut_10(struct intel_crtc_state *crtc_state, u32 prec_index) { Make "crtc_state" as const. >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >+ int hw_lut_size = ivb_lut_10_size(prec_index); >+ enum pipe pipe = crtc->pipe; >+ struct drm_property_blob *blob; >+ struct drm_color_lut *blob_data; >+ u32 i, val; >+ >+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | >+ PAL_PREC_AUTO_INCREMENT); >+ >+ blob = drm_property_create_blob(&dev_priv->drm, >+ sizeof(struct drm_color_lut) * hw_lut_size, Wrap this. >+ NULL); >+ if (IS_ERR(blob)) >+ return NULL; >+ >+ blob_data = blob->data; >+ >+ for (i = 0; i < hw_lut_size; i++) { >+ val = I915_READ(PREC_PAL_DATA(pipe)); >+ >+ blob_data[i].red = >intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10); >+ blob_data[i].green = >intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10); >+ blob_data[i].blue = >intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10); >+ } >+ >+ I915_WRITE(PREC_PAL_INDEX(pipe), 0); >+ >+ return blob; >+} >+ >+static void glk_read_luts(struct intel_crtc_state *crtc_state) { >+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) >+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); >+ else >+ crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, >+PAL_PREC_INDEX_VALUE(0)); } >+ > void intel_color_init(struct intel_crtc *crtc) { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -1727,9 >+1770,10 @@ void intel_color_init(struct intel_crtc *crtc) > > if (INTEL_GEN(dev_priv) >= 11) > dev_priv->display.load_luts = icl_load_luts; >- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) >+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { > dev_priv->display.load_luts = glk_load_luts; >- else if (INTEL_GEN(dev_priv) >= 8) >+ dev_priv->display.read_luts = glk_read_luts; >+ } else if (INTEL_GEN(dev_priv) >= 8) > dev_priv->display.load_luts = bdw_load_luts; > else if (INTEL_GEN(dev_priv) >= 7) > dev_priv->display.load_luts = ivb_load_luts; diff --git >a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index >acc9239..7613e14 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -10258,6 +10258,9 @@ enum skl_power_gate { > #define _PAL_PREC_GC_MAX_A 0x4A410 > #define _PAL_PREC_GC_MAX_B 0x4AC10 > #define _PAL_PREC_GC_MAX_C 0x4B410 >+#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) >+#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) >+#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) > #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 > #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 > #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 >-- >1.9.1
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4b9b28f..3762bdf 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1684,6 +1684,49 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) crtc_state->base.gamma_lut = ilk_read_gamma_lut(crtc_state); } +static struct drm_property_blob * +glk_read_lut_10(struct intel_crtc_state *crtc_state, u32 prec_index) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int hw_lut_size = ivb_lut_10_size(prec_index); + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *blob_data; + u32 i, val; + + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | + PAL_PREC_AUTO_INCREMENT); + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * hw_lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + blob_data = blob->data; + + for (i = 0; i < hw_lut_size; i++) { + val = I915_READ(PREC_PAL_DATA(pipe)); + + blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10); + blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10); + blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10); + } + + I915_WRITE(PREC_PAL_INDEX(pipe), 0); + + return blob; +} + +static void glk_read_luts(struct intel_crtc_state *crtc_state) +{ + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); + else + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -1727,9 +1770,10 @@ void intel_color_init(struct intel_crtc *crtc) if (INTEL_GEN(dev_priv) >= 11) dev_priv->display.load_luts = icl_load_luts; - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { dev_priv->display.load_luts = glk_load_luts; - else if (INTEL_GEN(dev_priv) >= 8) + dev_priv->display.read_luts = glk_read_luts; + } else if (INTEL_GEN(dev_priv) >= 8) dev_priv->display.load_luts = bdw_load_luts; else if (INTEL_GEN(dev_priv) >= 7) dev_priv->display.load_luts = ivb_load_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index acc9239..7613e14 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10258,6 +10258,9 @@ enum skl_power_gate { #define _PAL_PREC_GC_MAX_A 0x4A410 #define _PAL_PREC_GC_MAX_B 0x4AC10 #define _PAL_PREC_GC_MAX_C 0x4B410 +#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) +#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) +#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
For glk, have hw read out to create hw blob of gamma lut values. Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 48 ++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 ++ 2 files changed, 49 insertions(+), 2 deletions(-)