| Message ID | 20190829213321.4092-4-mike.leach@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: Fixes and updates for sysfs API | expand |
Hi Mike, On 29/08/2019 22:33, Mike Leach wrote: > TRCACATRn registers have match bits for secure and non-secure exception > levels which are not accessible by the sysfs API. > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. > Looks good to me. Some minor nits below. > Signed-off-by: Mike Leach <mike.leach@linaro.org> > --- > .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index cc8156318018..b520f3c1521f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, > } > static DEVICE_ATTR_RW(addr_context); > > +static ssize_t addr_exlevel_s_ns_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + u8 idx; > + unsigned long val; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct etmv4_config *config = &drvdata->config; > + > + spin_lock(&drvdata->spinlock); > + idx = config->addr_idx; > + val = BMVAL(config->addr_acc[idx], 14, 8); > + spin_unlock(&drvdata->spinlock); > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > +} > + > +static ssize_t addr_exlevel_s_ns_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + u8 idx; > + unsigned long val; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct etmv4_config *config = &drvdata->config; > + > + if (kstrtoul(buf, 16, &val)) > + return -EINVAL; Can this be 0 instead of 16 to accept any base ? > + > + if (val & ~0x7F) minor nit: Do we need to use (GENMASK(14, 8) >> 8) here instead of hard coding the mask ? > + return -EINVAL; > + > + spin_lock(&drvdata->spinlock); > + idx = config->addr_idx; > + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */ It may be worth adding a comment that bit[15] is RES0. > + config->addr_acc[idx] &= ~(GENMASK(14, 8)); > + config->addr_acc[idx] |= (val << 8); > + spin_unlock(&drvdata->spinlock); > + return size; > +} > +static DEVICE_ATTR_RW(addr_exlevel_s_ns); > + > static ssize_t seq_idx_show(struct device *dev, > struct device_attribute *attr, > char *buf) > @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { > &dev_attr_addr_stop.attr, > &dev_attr_addr_ctxtype.attr, > &dev_attr_addr_context.attr, > + &dev_attr_addr_exlevel_s_ns.attr, > &dev_attr_seq_idx.attr, > &dev_attr_seq_state.attr, > &dev_attr_seq_event.attr, Either ways, irrespective of the above comments : Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc8156318018..b520f3c1521f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t addr_exlevel_s_ns_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + val = BMVAL(config->addr_acc[idx], 14, 8); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_exlevel_s_ns_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + if (val & ~0x7F) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */ + config->addr_acc[idx] &= ~(GENMASK(14, 8)); + config->addr_acc[idx] |= (val << 8); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_exlevel_s_ns); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr,
TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Signed-off-by: Mike Leach <mike.leach@linaro.org> --- .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+)