| Message ID | 1567118827-26358-3-git-send-email-vdumpa@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Nvidia Arm SMMUv2 Implementation | expand |
On 30.8.2019 1.47, Krishna Reddy wrote: > Add binding doc for Nvidia's smmu-v2 implementation. > > Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > index 3133f3b..0de3759 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > @@ -17,6 +17,7 @@ conditions. > "arm,mmu-401" > "arm,mmu-500" > "cavium,smmu-v2" > + "nidia,smmu-v2" nvidia Mikko > "qcom,smmu-v2" > > depending on the particular implementation and/or the >
On 29/08/2019 23:47, Krishna Reddy wrote: > Add binding doc for Nvidia's smmu-v2 implementation. > > Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > index 3133f3b..0de3759 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt > @@ -17,6 +17,7 @@ conditions. > "arm,mmu-401" > "arm,mmu-500" > "cavium,smmu-v2" > + "nidia,smmu-v2" > "qcom,smmu-v2" I agree with Mikko that the compatible must be at least SoC-specific, but potentially even instance-specific (e.g. "nvidia,tegra194-gpu-smmu") depending on how many of these parallel-SMMU configurations might be hiding in current and future SoCs. Robin. > > depending on the particular implementation and/or the >
>> + "nidia,smmu-v2" >> "qcom,smmu-v2" >I agree with Mikko that the compatible must be at least SoC-specific, but potentially even instance-specific (e.g. "nvidia,tegra194-gpu-smmu") > depending on how many of these parallel-SMMU configurations might be hiding in current and future SoCs. I am correcting the spelling mistake pointed by Mikko. The NVIDIA SMMUv2 implementation is getting used beyond Tegra194 SOC. To be able to use the smmu compatible string across multiple SOC's, "nvidia,smmu-v2" compatible string is chosen. Are you suggesting to make it soc specific and add another one in future? -KR
On Fri, Aug 30, 2019 at 06:12:08PM +0000, Krishna Reddy wrote: > >> + "nidia,smmu-v2" > >> "qcom,smmu-v2" > > >I agree with Mikko that the compatible must be at least SoC-specific, but potentially even instance-specific (e.g. "nvidia,tegra194-gpu-smmu") > > depending on how many of these parallel-SMMU configurations might be hiding in current and future SoCs. > > I am correcting the spelling mistake pointed by Mikko. The NVIDIA SMMUv2 implementation is getting used beyond Tegra194 SOC. > To be able to use the smmu compatible string across multiple SOC's, "nvidia,smmu-v2" compatible string is chosen. > Are you suggesting to make it soc specific and add another one in future? Yeah, I think that's the safest thing to do. Even if we're using the same implementation in future SoCs, chances are there will be some changes. Even if the changes are just fixes, having a SoC-specific compatible string will ensure we can apply workarounds only to the implementations that are missing the fixes. So I think "nvidia,tegra194-smmu" is a good candidate. It uniquely identifies the instantiation of the IP in Tegra194. Also, if it ever turns out that the instantiation of the SMMU in the next Tegra generation is *exactly* the same (even if highly unlikely), there's nothing wrong with reusing the "nvidia,tegra194-smmu". We've done similar things in the past, where some new IP was mostly compatible with old IP. Typically we still include a new compatible string in case any errata are discovered subsequently. It's not uncommon to see things like: compatible = "nvidia,tegra124-xyz", "nvidia,tegra20-xyz"; Basically this means that this is the IP that was also used in Tegra20 and the same Tegra20 driver can be used to drive this hardware on Tegra124. The Tegra124-specific compatible string may enable newer features if there's a driver that supports it. Thierry
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 3133f3b..0de3759 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,6 +17,7 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "nidia,smmu-v2" "qcom,smmu-v2" depending on the particular implementation and/or the
Add binding doc for Nvidia's smmu-v2 implementation. Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+)