[v2] arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
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Message ID 1567124807-199633-1-git-send-email-shawn.lin@rock-chips.com
State New
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  • [v2] arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
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Commit Message

Shawn Lin Aug. 30, 2019, 12:26 a.m. UTC
150MHz is a fundamental limitation of RK3288 Soc, w/o this limitation,
eMMC, for instance, will run into 200MHz clock rate in HS200 mode, which
makes the RK3328 boards not always boot properly. By adding it in
rk3328.dtsi would also obviate the worry of missing it when adding new
boards.

Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs")
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Liang Chen <cl@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

---

Not a strickly fix patch but add fixes tag in hope for stable
kernel maintainers would help backport it.

Changes in v2:
- move the limitation in rk3288.dtsi

 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++
 1 file changed, 3 insertions(+)

Comments

Heiko Stuebner Sept. 1, 2019, 4:30 a.m. UTC | #1
Hi Shawn,

Am Freitag, 30. August 2019, 02:26:47 CEST schrieb Shawn Lin:
> 150MHz is a fundamental limitation of RK3288 Soc, w/o this limitation,

I've fixed the rk3288 -> rk3328 above and applied the patch for 5.4
together with a "cc-stable" tag.


Thanks
Heiko

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 4a175ff..31cc154 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -813,6 +813,7 @@ 
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
 		status = "disabled";
 	};
 
@@ -824,6 +825,7 @@ 
 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
 		status = "disabled";
 	};
 
@@ -835,6 +837,7 @@ 
 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
 		status = "disabled";
 	};