@@ -609,6 +609,32 @@ GS_DECLARE_RW_REG(imr, imr);
GS_DECLARE_RW_REG(busdir, busdir);
GS_DECLARE_RW_REG(siglblid, siglblid);
+#define GS_WS_REG(reg, str, ...) \
+ gs_write_##reg((struct gs_##str) { __VA_ARGS__ })
+
+/**
+ * DOC:
+ *
+ * The Graphics Synthesizer write macros simplifies register writing,
+ * allowing named fields in statements such as GS_WRITE_CSR( .flush = 1 ).
+ *
+ * The following registers have macros: PMODE, SMODE1, SMODE2, SRFSH, SYNCH1,
+ * SYNCH2, SYNCV, DISPLAY1, DISPLAY2, DISPFB1, DISPFB2, CSR and BUSDIR.
+ */
+#define GS_WRITE_PMODE(...) GS_WS_REG(pmode, pmode, __VA_ARGS__)
+#define GS_WRITE_SMODE1(...) GS_WS_REG(smode1, smode1, __VA_ARGS__)
+#define GS_WRITE_SMODE2(...) GS_WS_REG(smode2, smode2, __VA_ARGS__)
+#define GS_WRITE_SRFSH(...) GS_WS_REG(srfsh, srfsh, __VA_ARGS__)
+#define GS_WRITE_SYNCH1(...) GS_WS_REG(synch1, synch1, __VA_ARGS__)
+#define GS_WRITE_SYNCH2(...) GS_WS_REG(synch2, synch2, __VA_ARGS__)
+#define GS_WRITE_SYNCV(...) GS_WS_REG(syncv, syncv, __VA_ARGS__)
+#define GS_WRITE_DISPLAY1(...) GS_WS_REG(display1, display, __VA_ARGS__)
+#define GS_WRITE_DISPLAY2(...) GS_WS_REG(display2, display, __VA_ARGS__)
+#define GS_WRITE_DISPFB1(...) GS_WS_REG(dispfb1, dispfb, __VA_ARGS__)
+#define GS_WRITE_DISPFB2(...) GS_WS_REG(dispfb2, dispfb, __VA_ARGS__)
+#define GS_WRITE_CSR(...) GS_WS_REG(csr, csr, __VA_ARGS__)
+#define GS_WRITE_BUSDIR(...) GS_WS_REG(busdir, busdir, __VA_ARGS__)
+
/**
* gs_xorq_imr - exclusive or (XOR) value with the IMR register
* @value: value to XOR with the IMR register
The Graphics Synthesizer write macros simplifies register writing, allowing named fields in statements such as GS_WRITE_CSR( .flush = 1 ). The following registers have macros: PMODE, SMODE1, SMODE2, SRFSH, SYNCH1, SYNCH2, SYNCV, DISPLAY1, DISPLAY2, DISPFB1, DISPFB2, CSR and BUSDIR. Signed-off-by: Fredrik Noring <noring@nocrew.org> --- arch/mips/include/asm/mach-ps2/gs-registers.h | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)