| Message ID | 1567603943-25316-2-git-send-email-talel@amazon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Amazon's Annapurna Labs Memory Controller EDAC | expand |
On Wed, Sep 04, 2019 at 04:32:21PM +0300, Talel Shenhar wrote: > Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding. > > Signed-off-by: Talel Shenhar <talel@amazon.com> > --- > .../devicetree/bindings/edac/amazon,al-mc-edac.txt | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt > > diff --git a/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt > new file mode 100644 > index 0000000..9a3803f > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt > @@ -0,0 +1,24 @@ > +Amazon's Annapurna Labs Memory Controller EDAC > + > +EDAC node is defined to describe on-chip error detection and correction for > +Amazon's Annapurna Labs Memory Controller. > + > +Required properties: > +- compatible: Shall be "amazon,al-mc-edac". > +- reg: DDR controller resource. > + > +Optional: > +- interrupt-names: may include "ue", for uncorrectable errors, > + and/or "ce", for correctable errors. > +- interrupts: should contain the interrupts associated with the > + interrupts names. > + > +Example: > + > +al_mc_edac { edac@f0080000 With that, Reviewed-by: Rob Herring <robh@kernel.org> > + compatible = "amazon,al-mc-edac"; > + reg = <0x0 0xf0080000 0x0 0x00010000>; > + interrupt-parent = <&amazon_al_system_fabric>; > + interrupt-names = "ue"; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > +}; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt new file mode 100644 index 0000000..9a3803f --- /dev/null +++ b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt @@ -0,0 +1,24 @@ +Amazon's Annapurna Labs Memory Controller EDAC + +EDAC node is defined to describe on-chip error detection and correction for +Amazon's Annapurna Labs Memory Controller. + +Required properties: +- compatible: Shall be "amazon,al-mc-edac". +- reg: DDR controller resource. + +Optional: +- interrupt-names: may include "ue", for uncorrectable errors, + and/or "ce", for correctable errors. +- interrupts: should contain the interrupts associated with the + interrupts names. + +Example: + +al_mc_edac { + compatible = "amazon,al-mc-edac"; + reg = <0x0 0xf0080000 0x0 0x00010000>; + interrupt-parent = <&amazon_al_system_fabric>; + interrupt-names = "ue"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; +};
Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding. Signed-off-by: Talel Shenhar <talel@amazon.com> --- .../devicetree/bindings/edac/amazon,al-mc-edac.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-mc-edac.txt