| Message ID | 20190906122314.2146-1-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915: Use engine relative LRIs on context setup | expand |
Patchwork <patchwork@emeril.freedesktop.org> writes: > == Series Details == > > Series: series starting with [1/2] drm/i915: Use engine relative LRIs on context setup > URL : https://patchwork.freedesktop.org/series/66335/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14302 > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/ > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_14302: > > ### IGT changes ### > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * igt@gem_sync@basic-all: > - {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-tgl-u/igt@gem_sync@basic-all.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_14302 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_exec@basic: > - fi-apl-guc: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-apl-guc/igt@gem_ctx_exec@basic.html > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-apl-guc/igt@gem_ctx_exec@basic.html > > * igt@gem_ctx_switch@rcs0: > - fi-icl-u2: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713]) > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u2/igt@gem_ctx_switch@rcs0.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u2/igt@gem_ctx_switch@rcs0.html Ok, disturbing enough. I will send v2 with relative offsets turned off on icl. Chris has selftest cooking so we can experiment with icl/cs_mmio on later time. -Mika > > * igt@kms_addfb_basic@tile-pitch-mismatch: > - fi-icl-u3: [PASS][6] -> [DMESG-WARN][7] ([fdo#107724]) +1 similar issue > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@kms_addfb_basic@tile-pitch-mismatch.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u3/igt@kms_addfb_basic@tile-pitch-mismatch.html > > > #### Possible fixes #### > > * igt@i915_pm_rpm@basic-rte: > - {fi-icl-guc}: [DMESG-WARN][8] -> [PASS][9] > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-guc/igt@i915_pm_rpm@basic-rte.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-guc/igt@i915_pm_rpm@basic-rte.html > > * igt@i915_selftest@live_execlists: > - fi-skl-gvtdvm: [DMESG-FAIL][10] ([fdo#111108]) -> [PASS][11] > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html > > * igt@kms_chamelium@dp-crc-fast: > - fi-cml-u2: [FAIL][12] ([fdo#110627]) -> [PASS][13] > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html > > * igt@kms_frontbuffer_tracking@basic: > - {fi-icl-u4}: [FAIL][14] ([fdo#103167]) -> [PASS][15] > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html > > * igt@vgem_basic@unload: > - fi-icl-u3: [DMESG-WARN][16] ([fdo#107724]) -> [PASS][17] > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@vgem_basic@unload.html > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u3/igt@vgem_basic@unload.html > > > #### Warnings #### > > * igt@kms_chamelium@hdmi-hpd-fast: > - fi-kbl-7500u: [FAIL][18] ([fdo#111407]) -> [FAIL][19] ([fdo#111096]) > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 > [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 > [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 > [fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627 > [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 > [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108 > [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 > > > Participating hosts (53 -> 45) > ------------------------------ > > Additional (1): fi-tgl-u > Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * Linux: CI_DRM_6841 -> Patchwork_14302 > > CI-20190529: 20190529 > CI_DRM_6841: 5c24bcfb9c6036b32dbfdbc22d773473880ff498 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_14302: 5f5d80a3dd019803bbba7d685805bade4a33d54c @ git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > 5f5d80a3dd01 drm/i915/tgl: Register state context definition for Gen12 > 0441c15504e2 drm/i915: Use engine relative LRIs on context setup > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 15e02cb58a67..943f0663837e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -481,6 +481,7 @@ struct intel_engine_cs { #define I915_ENGINE_HAS_SEMAPHORES BIT(3) #define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4) #define I915_ENGINE_IS_VIRTUAL BIT(5) +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6) unsigned int flags; /* @@ -576,6 +577,12 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_IS_VIRTUAL; } +static inline bool +intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine) +{ + return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO; +} + #define instdone_has_slice(dev_priv___, sseu___, slice___) \ ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___)) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 86e00a2db8a4..e1b87a516ef8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -132,6 +132,8 @@ * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) +/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12:2) : offset) */ +#define MI_LRI_CS_MMIO (1<<19) #define MI_LRI_FORCE_POSTED (1<<12) #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 87b7473a6dfb..6c68ed2bf3d2 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1214,7 +1214,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) unsigned int n; GEM_BUG_ON(READ_ONCE(ve->context.inflight)); - virtual_update_register_offsets(regs, engine); + + if (!intel_engine_has_relative_mmio(engine)) + virtual_update_register_offsets(regs, + engine); if (!list_empty(&ve->context.signals)) virtual_xfer_breadcrumbs(ve, engine); @@ -2939,6 +2942,10 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) engine->flags |= I915_ENGINE_HAS_PREEMPTION; } + + engine->flags |= (engine->class != COPY_ENGINE_CLASS && + INTEL_GEN(engine->i915) >= 11) ? + I915_ENGINE_HAS_RELATIVE_MMIO : 0; } static void execlists_destroy(struct intel_engine_cs *engine) @@ -3130,8 +3137,10 @@ static void execlists_init_reg_state(u32 *regs, struct intel_ring *ring) { struct i915_ppgtt *ppgtt = vm_alias(ce->vm); - bool rcs = engine->class == RENDER_CLASS; - u32 base = engine->mmio_base; + const bool rcs = engine->class == RENDER_CLASS; + const u32 base = engine->mmio_base; + const u32 lri_base = intel_engine_has_relative_mmio(engine) ? + MI_LRI_CS_MMIO : 0; /* * A context is actually a big batch buffer with several @@ -3144,7 +3153,7 @@ static void execlists_init_reg_state(u32 *regs, * Must keep consistent with virtual_update_register_offsets(). */ regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | - MI_LRI_FORCE_POSTED; + MI_LRI_FORCE_POSTED | lri_base; CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base), _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | @@ -3191,7 +3200,8 @@ static void execlists_init_reg_state(u32 *regs, } } - regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; + regs[CTX_LRI_HEADER_1] = + MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED | lri_base; CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); /* PDP values well be assigned later if needed */ @@ -3218,7 +3228,7 @@ static void execlists_init_reg_state(u32 *regs, } if (rcs) { - regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); + regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1) | lri_base; CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); } @@ -3411,8 +3421,9 @@ static void virtual_engine_initial_hint(struct virtual_engine *ve) return; swap(ve->siblings[swp], ve->siblings[0]); - virtual_update_register_offsets(ve->context.lrc_reg_state, - ve->siblings[0]); + if (!intel_engine_has_relative_mmio(ve->siblings[0])) + virtual_update_register_offsets(ve->context.lrc_reg_state, + ve->siblings[0]); } static int virtual_context_pin(struct intel_context *ce)
Daniele pointed out that relative mmio works differently in on context restore. Instead of adding the engine mmio base to offset, it masks out the base and adds bits [12:2] to current engine base. This should allow us to construct context register state to be applicable to all instances, including virtual. And avoid the trouble of updating the registers on virtual instances when submitting work. Bspec: 20206 Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 +++++ drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 ++ drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++++++++++++++------ 3 files changed, 28 insertions(+), 8 deletions(-)