[1/3] x86: drop CONFIG_X86_MCE_THERMAL

Commit Message

Jan Beulich Sept. 6, 2019, 2 p.m. UTC

There's no point having this if it's not exposed through Kconfig.

Take the liberty and also drop an unnecessary "return" in context.

Signed-off-by: Jan Beulich <[e-mail]>

Comments

Andrew Cooper Sept. 6, 2019, 2:01 p.m. UTC | #1

On 06/09/2019 15:00, Jan Beulich wrote:
> There's no point having this if it's not exposed through Kconfig.
>
> Take the liberty and also drop an unnecessary "return" in context.
>
> Signed-off-by: Jan Beulich <[e-mail]>

Acked-by: Andrew Cooper <[e-mail]>

Patch

--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -189,19 +189,15 @@  void clear_local_APIC(void)
         v = apic_read(APIC_LVTPC);
         apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
     }
-
-/* lets not touch this if we didn't frob it */
-#ifdef CONFIG_X86_MCE_THERMAL
     if (maxlvt >= 5) {
         v = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
     }
-#endif
-
     if (maxlvt >= 6) {
         v = apic_read(APIC_CMCI);
         apic_write(APIC_CMCI, v | APIC_LVT_MASKED);
     }
+
     /*
      * Clean APIC state for other OSs:
      */
@@ -212,11 +208,8 @@  void clear_local_APIC(void)
         apic_write(APIC_LVTERR, APIC_LVT_MASKED);
     if (maxlvt >= 4)
         apic_write(APIC_LVTPC, APIC_LVT_MASKED);
-
-#ifdef CONFIG_X86_MCE_THERMAL
     if (maxlvt >= 5)
         apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
-#endif
     if (maxlvt >= 6)
         apic_write(APIC_CMCI, APIC_LVT_MASKED);
 
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -51,7 +51,6 @@  bool __read_mostly lmce_support;
 #define INTEL_SRAR_DATA_LOAD	0x134
 #define INTEL_SRAR_INSTR_FETCH	0x150
 
-#ifdef CONFIG_X86_MCE_THERMAL
 #define MCE_RING                0x1
 static DEFINE_PER_CPU(int, last_state);
 
@@ -174,9 +173,7 @@  static void intel_init_thermal(struct cp
     if ( opt_cpu_info )
         printk(KERN_INFO "CPU%u: Thermal monitoring enabled (%s)\n",
                cpu, tm2 ? "TM2" : "TM1");
-    return;
 }
-#endif /* CONFIG_X86_MCE_THERMAL */
 
 /* Intel MCE handler */
 static inline void intel_get_extended_msr(struct mcinfo_extended *ext, u32 msr)
@@ -941,9 +938,8 @@  enum mcheck_type intel_mcheck_init(struc
     intel_init_mce();
 
     intel_init_cmci(c);
-#ifdef CONFIG_X86_MCE_THERMAL
+
     intel_init_thermal(c);
-#endif
 
     return mcheck_intel;
 }
--- a/xen/include/asm-x86/config.h
+++ b/xen/include/asm-x86/config.h
@@ -21,7 +21,6 @@ 
 
 #define CONFIG_X86_PM_TIMER 1
 #define CONFIG_HPET_TIMER 1
-#define CONFIG_X86_MCE_THERMAL 1
 #define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1
 #define CONFIG_DISCONTIGMEM 1
 #define CONFIG_NUMA_EMU 1