From patchwork Fri Sep 6 14:00:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 11135327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB7D71398 for ; Fri, 6 Sep 2019 14:03:34 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D110F2070C for ; Fri, 6 Sep 2019 14:03:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D110F2070C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1i6En1-0006Sj-Td; Fri, 06 Sep 2019 14:00:39 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1i6Emz-0006Se-VN for xen-devel@lists.xenproject.org; Fri, 06 Sep 2019 14:00:37 +0000 X-Inumbo-ID: b38426a0-d0ae-11e9-978d-bc764e2007e4 Received: from mx1.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id b38426a0-d0ae-11e9-978d-bc764e2007e4; Fri, 06 Sep 2019 14:00:37 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 3840FB0E2; Fri, 6 Sep 2019 14:00:36 +0000 (UTC) From: Jan Beulich To: "xen-devel@lists.xenproject.org" References: <67f6d8cc-05cf-ac8e-38c0-55578f9f595a@suse.com> Message-ID: Date: Fri, 6 Sep 2019 16:00:44 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <67f6d8cc-05cf-ac8e-38c0-55578f9f595a@suse.com> Content-Language: en-US Subject: [Xen-devel] [PATCH 1/3] x86: drop CONFIG_X86_MCE_THERMAL X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" There's no point having this if it's not exposed through Kconfig. Take the liberty and also drop an unnecessary "return" in context. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -189,19 +189,15 @@ void clear_local_APIC(void) v = apic_read(APIC_LVTPC); apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); } - -/* lets not touch this if we didn't frob it */ -#ifdef CONFIG_X86_MCE_THERMAL if (maxlvt >= 5) { v = apic_read(APIC_LVTTHMR); apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); } -#endif - if (maxlvt >= 6) { v = apic_read(APIC_CMCI); apic_write(APIC_CMCI, v | APIC_LVT_MASKED); } + /* * Clean APIC state for other OSs: */ @@ -212,11 +208,8 @@ void clear_local_APIC(void) apic_write(APIC_LVTERR, APIC_LVT_MASKED); if (maxlvt >= 4) apic_write(APIC_LVTPC, APIC_LVT_MASKED); - -#ifdef CONFIG_X86_MCE_THERMAL if (maxlvt >= 5) apic_write(APIC_LVTTHMR, APIC_LVT_MASKED); -#endif if (maxlvt >= 6) apic_write(APIC_CMCI, APIC_LVT_MASKED); --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -51,7 +51,6 @@ bool __read_mostly lmce_support; #define INTEL_SRAR_DATA_LOAD 0x134 #define INTEL_SRAR_INSTR_FETCH 0x150 -#ifdef CONFIG_X86_MCE_THERMAL #define MCE_RING 0x1 static DEFINE_PER_CPU(int, last_state); @@ -174,9 +173,7 @@ static void intel_init_thermal(struct cp if ( opt_cpu_info ) printk(KERN_INFO "CPU%u: Thermal monitoring enabled (%s)\n", cpu, tm2 ? "TM2" : "TM1"); - return; } -#endif /* CONFIG_X86_MCE_THERMAL */ /* Intel MCE handler */ static inline void intel_get_extended_msr(struct mcinfo_extended *ext, u32 msr) @@ -941,9 +938,8 @@ enum mcheck_type intel_mcheck_init(struc intel_init_mce(); intel_init_cmci(c); -#ifdef CONFIG_X86_MCE_THERMAL + intel_init_thermal(c); -#endif return mcheck_intel; } --- a/xen/include/asm-x86/config.h +++ b/xen/include/asm-x86/config.h @@ -21,7 +21,6 @@ #define CONFIG_X86_PM_TIMER 1 #define CONFIG_HPET_TIMER 1 -#define CONFIG_X86_MCE_THERMAL 1 #define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1 #define CONFIG_DISCONTIGMEM 1 #define CONFIG_NUMA_EMU 1