| Message ID | 20190907072111.31132-2-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/framebuffer: Format modifier for Intel Gen-12 render compression | expand |
On Sat, Sep 07, 2019 at 12:21:11AM -0700, Dhinakaran Pandiyan wrote: > Gen-12 display decompression operates on Y-tiled compressed main surface. > The CCS is linear and has 4 bits of metadata for each main surface cache > line pair, a size ratio of 1:256. Gen-12 display decompression is > incompatible with buffers compressed by earlier GPUs, so make use of a new > modifier to identify gen-12 compression. Another notable change is that > render decompression is supported on all planes except cursor and on all > pipes. Start by adding render decompression support for [A,X]BGR888 pixel > formats. > > v2: Fix checkpatch warnings (Lucas) > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Nanley G Chery <nanley.g.chery@intel.com> > Cc: Jason Ekstrand <jason@jlekstrand.net> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++--- > drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++--- > 2 files changed, 71 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 3b5275ab66cf..303e1d2e97a6 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > if (color_plane == 1) > return 128; > /* fall through */ > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + if (color_plane == 1) > + return cpp; If the CCS surface itself is linear is there a reason we don't treat this like a regular linear surface and return intel_tile_size() = 4096? > + /* fall through */ > case I915_FORMAT_MOD_Y_TILED: > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) > return 128; > @@ -2044,6 +2048,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, > if (INTEL_GEN(dev_priv) >= 9) > return 256 * 1024; > return 0; > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + return 4 * 4 * 1024; The bspec just says "must be 16KB aligned" so I think it would be more natural to just write this as 16 * 1024? > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Yf_TILED_CCS: > case I915_FORMAT_MOD_Y_TILED: > @@ -2243,7 +2249,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y, > > static bool is_surface_linear(u64 modifier, int color_plane) > { > - return modifier == DRM_FORMAT_MOD_LINEAR; > + return modifier == DRM_FORMAT_MOD_LINEAR || > + (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1); > } > > static u32 intel_adjust_aligned_offset(int *x, int *y, > @@ -2430,6 +2437,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) > return I915_TILING_X; > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Y_TILED_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > return I915_TILING_Y; > default: > return I915_TILING_NONE; > @@ -2450,7 +2458,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) > * us a ratio of one byte in the CCS for each 8x16 pixels in the > * main surface. > */ > -static const struct drm_format_info ccs_formats[] = { > +static const struct drm_format_info skl_ccs_formats[] = { > { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, > @@ -2461,6 +2469,24 @@ static const struct drm_format_info ccs_formats[] = { > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, > }; > > +/* > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in > + * the main surface. > + */ > +static const struct drm_format_info gen12_ccs_formats[] = { > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, > + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, }, > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, > + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, }, > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, > + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, > + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > +}; > + > static const struct drm_format_info * > lookup_format_info(const struct drm_format_info formats[], > int num_formats, u32 format) > @@ -2481,8 +2507,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) > switch (cmd->modifier[0]) { > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Yf_TILED_CCS: > - return lookup_format_info(ccs_formats, > - ARRAY_SIZE(ccs_formats), > + return lookup_format_info(skl_ccs_formats, > + ARRAY_SIZE(skl_ccs_formats), > + cmd->pixel_format); > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + return lookup_format_info(gen12_ccs_formats, > + ARRAY_SIZE(gen12_ccs_formats), > cmd->pixel_format); > default: > return NULL; > @@ -2491,7 +2521,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) > > bool is_ccs_modifier(u64 modifier) > { > - return modifier == I915_FORMAT_MOD_Y_TILED_CCS || > + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > + modifier == I915_FORMAT_MOD_Y_TILED_CCS || > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > } > > @@ -2660,7 +2691,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, > int main_x, main_y; > int ccs_x, ccs_y; > > - intel_tile_dims(fb, i, &tile_width, &tile_height); > + if (!is_surface_linear(fb->modifier, i)) { > + intel_tile_dims(fb, i, &tile_width, &tile_height); > + } else { > + tile_width = 64 / cpp; > + tile_height = 1; > + } > + > tile_width *= hsub; > tile_height *= vsub; > > @@ -4054,6 +4091,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > case I915_FORMAT_MOD_Y_TILED: > return PLANE_CTL_TILED_Y; > case I915_FORMAT_MOD_Y_TILED_CCS: > + /* fall through */ > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > case I915_FORMAT_MOD_Yf_TILED: > return PLANE_CTL_TILED_YF; > @@ -9829,7 +9868,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, > case PLANE_CTL_TILED_Y: > plane_config->tiling = I915_TILING_Y; > if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > - fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; > + fb->modifier = INTEL_GEN(dev_priv) >= 12 ? > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : > + I915_FORMAT_MOD_Y_TILED_CCS; > else > fb->modifier = I915_FORMAT_MOD_Y_TILED; > break; > @@ -15746,6 +15787,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, > is_ccs_modifier(fb->modifier)) > stride_alignment *= 4; > > + /* > + * The main surface pitch must be padded to a multiple of four > + * tile widths. > + */ > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && > + i == 0) > + stride_alignment *= 4; > + Shouldn't we handle this logic right inside intel_fb_stride_alignment and make it more explicit? if (...) stride_alignment = 4 * intel_tile_width_bytes(...) I know we handle a hardware WA outside the function since that's more of a special case, but doing that for the regular behavior of render compression seems to make the logic harder to follow. Matt > if (fb->pitches[i] & (stride_alignment - 1)) { > DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", > i, fb->pitches[i], stride_alignment); > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > index e415b0ad4a42..7b1087f71d6b 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane, > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; > u32 surf_addr = plane_state->color_plane[color_plane].offset; > u32 stride = skl_plane_stride(plane_state, color_plane); > + u32 aux_dist = plane_state->color_plane[1].offset - surf_addr; > u32 aux_stride = skl_plane_stride(plane_state, 1); > int crtc_x = plane_state->base.dst.x1; > int crtc_y = plane_state->base.dst.y1; > @@ -588,8 +589,10 @@ skl_program_plane(struct intel_plane *plane, > I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); > I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); > I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); > - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), > - (plane_state->color_plane[1].offset - surf_addr) | aux_stride); > + > + if (INTEL_GEN(dev_priv) < 12) > + aux_dist |= aux_stride; > + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist); > > if (icl_is_hdr_plane(dev_priv, plane_id)) { > u32 cus_ctl = 0; > @@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, > (fb->modifier == I915_FORMAT_MOD_Y_TILED || > fb->modifier == I915_FORMAT_MOD_Yf_TILED || > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || > - fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) { > + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) { > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); > return -EINVAL; > } > @@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = { > DRM_FORMAT_MOD_INVALID > }; > > -static const u64 gen12_plane_format_modifiers_noccs[] = { > +static const u64 gen12_plane_format_modifiers_ccs[] = { > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > I915_FORMAT_MOD_Y_TILED, > I915_FORMAT_MOD_X_TILED, > DRM_FORMAT_MOD_LINEAR, > @@ -2319,6 +2324,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_MOD_LINEAR: > case I915_FORMAT_MOD_X_TILED: > case I915_FORMAT_MOD_Y_TILED: > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > break; > default: > return false; > @@ -2329,6 +2335,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_XBGR8888: > case DRM_FORMAT_ARGB8888: > case DRM_FORMAT_ABGR8888: > + if (is_ccs_modifier(modifier)) > + return true; > + /* fall through */ > case DRM_FORMAT_RGB565: > case DRM_FORMAT_XRGB2101010: > case DRM_FORMAT_XBGR2101010: > @@ -2537,13 +2546,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > formats = skl_get_plane_formats(dev_priv, pipe, > plane_id, &num_formats); > > + plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); > if (INTEL_GEN(dev_priv) >= 12) { > - /* TODO: Implement support for gen-12 CCS modifiers */ > - plane->has_ccs = false; > - modifiers = gen12_plane_format_modifiers_noccs; > + modifiers = gen12_plane_format_modifiers_ccs; > plane_funcs = &gen12_plane_funcs; > } else { > - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); > if (plane->has_ccs) > modifiers = skl_plane_format_modifiers_ccs; > else > -- > 2.17.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3b5275ab66cf..303e1d2e97a6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) if (color_plane == 1) return 128; /* fall through */ + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + if (color_plane == 1) + return cpp; + /* fall through */ case I915_FORMAT_MOD_Y_TILED: if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; @@ -2044,6 +2048,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, if (INTEL_GEN(dev_priv) >= 9) return 256 * 1024; return 0; + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + return 4 * 4 * 1024; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: case I915_FORMAT_MOD_Y_TILED: @@ -2243,7 +2249,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y, static bool is_surface_linear(u64 modifier, int color_plane) { - return modifier == DRM_FORMAT_MOD_LINEAR; + return modifier == DRM_FORMAT_MOD_LINEAR || + (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1); } static u32 intel_adjust_aligned_offset(int *x, int *y, @@ -2430,6 +2437,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) return I915_TILING_X; case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: return I915_TILING_Y; default: return I915_TILING_NONE; @@ -2450,7 +2458,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) * us a ratio of one byte in the CCS for each 8x16 pixels in the * main surface. */ -static const struct drm_format_info ccs_formats[] = { +static const struct drm_format_info skl_ccs_formats[] = { { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, @@ -2461,6 +2469,24 @@ static const struct drm_format_info ccs_formats[] = { .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, }; +/* + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in + * the main surface. + */ +static const struct drm_format_info gen12_ccs_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, +}; + static const struct drm_format_info * lookup_format_info(const struct drm_format_info formats[], int num_formats, u32 format) @@ -2481,8 +2507,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) switch (cmd->modifier[0]) { case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: - return lookup_format_info(ccs_formats, - ARRAY_SIZE(ccs_formats), + return lookup_format_info(skl_ccs_formats, + ARRAY_SIZE(skl_ccs_formats), + cmd->pixel_format); + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + return lookup_format_info(gen12_ccs_formats, + ARRAY_SIZE(gen12_ccs_formats), cmd->pixel_format); default: return NULL; @@ -2491,7 +2521,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) bool is_ccs_modifier(u64 modifier) { - return modifier == I915_FORMAT_MOD_Y_TILED_CCS || + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_CCS || modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -2660,7 +2691,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, int main_x, main_y; int ccs_x, ccs_y; - intel_tile_dims(fb, i, &tile_width, &tile_height); + if (!is_surface_linear(fb->modifier, i)) { + intel_tile_dims(fb, i, &tile_width, &tile_height); + } else { + tile_width = 64 / cpp; + tile_height = 1; + } + tile_width *= hsub; tile_height *= vsub; @@ -4054,6 +4091,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) case I915_FORMAT_MOD_Y_TILED: return PLANE_CTL_TILED_Y; case I915_FORMAT_MOD_Y_TILED_CCS: + /* fall through */ + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; case I915_FORMAT_MOD_Yf_TILED: return PLANE_CTL_TILED_YF; @@ -9829,7 +9868,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, case PLANE_CTL_TILED_Y: plane_config->tiling = I915_TILING_Y; if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) - fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; + fb->modifier = INTEL_GEN(dev_priv) >= 12 ? + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : + I915_FORMAT_MOD_Y_TILED_CCS; else fb->modifier = I915_FORMAT_MOD_Y_TILED; break; @@ -15746,6 +15787,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, is_ccs_modifier(fb->modifier)) stride_alignment *= 4; + /* + * The main surface pitch must be padded to a multiple of four + * tile widths. + */ + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && + i == 0) + stride_alignment *= 4; + if (fb->pitches[i] & (stride_alignment - 1)) { DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", i, fb->pitches[i], stride_alignment); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e415b0ad4a42..7b1087f71d6b 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane, const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 surf_addr = plane_state->color_plane[color_plane].offset; u32 stride = skl_plane_stride(plane_state, color_plane); + u32 aux_dist = plane_state->color_plane[1].offset - surf_addr; u32 aux_stride = skl_plane_stride(plane_state, 1); int crtc_x = plane_state->base.dst.x1; int crtc_y = plane_state->base.dst.y1; @@ -588,8 +589,10 @@ skl_program_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), - (plane_state->color_plane[1].offset - surf_addr) | aux_stride); + + if (INTEL_GEN(dev_priv) < 12) + aux_dist |= aux_stride; + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist); if (icl_is_hdr_plane(dev_priv, plane_id)) { u32 cus_ctl = 0; @@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, (fb->modifier == I915_FORMAT_MOD_Y_TILED || fb->modifier == I915_FORMAT_MOD_Yf_TILED || fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || - fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) { + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) { DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); return -EINVAL; } @@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = { DRM_FORMAT_MOD_INVALID }; -static const u64 gen12_plane_format_modifiers_noccs[] = { +static const u64 gen12_plane_format_modifiers_ccs[] = { + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR, @@ -2319,6 +2324,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: break; default: return false; @@ -2329,6 +2335,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ABGR8888: + if (is_ccs_modifier(modifier)) + return true; + /* fall through */ case DRM_FORMAT_RGB565: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: @@ -2537,13 +2546,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, formats = skl_get_plane_formats(dev_priv, pipe, plane_id, &num_formats); + plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); if (INTEL_GEN(dev_priv) >= 12) { - /* TODO: Implement support for gen-12 CCS modifiers */ - plane->has_ccs = false; - modifiers = gen12_plane_format_modifiers_noccs; + modifiers = gen12_plane_format_modifiers_ccs; plane_funcs = &gen12_plane_funcs; } else { - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); if (plane->has_ccs) modifiers = skl_plane_format_modifiers_ccs; else