[v7,1/7] drm/i915/tgl: Add DC3CO required register and bits
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Message ID 20190907171443.16181-2-anshuman.gupta@intel.com
State New
Headers show
Series
  • DC3CO Support for TGL
Related show

Commit Message

Anshuman Gupta Sept. 7, 2019, 5:14 p.m. UTC
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Manna, Animesh Sept. 11, 2019, 9:08 a.m. UTC | #1
On 9/7/2019 10:44 PM, Anshuman Gupta wrote:
> Adding following definition to i915_reg.h
> 1. DC_STATE_EN register DC3CO bit fields and masks.
> 2. Transcoder EXITLINE register and its bit fields and mask.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 006cffd56be2..273a4ed8b3e9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4135,6 +4135,7 @@ enum {
>   #define _VTOTAL_A	0x6000c
>   #define _VBLANK_A	0x60010
>   #define _VSYNC_A	0x60014
> +#define _EXITLINE_A	0x60018
>   #define _PIPEASRC	0x6001c
>   #define _BCLRPAT_A	0x60020
>   #define _VSYNCSHIFT_A	0x60028
> @@ -4181,11 +4182,16 @@ enum {
>   #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
>   #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
>   #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
> +#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
>   #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
>   #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
>   #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
>   #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
>   
> +#define  EXITLINE_ENABLE	(1 << 31)

Need one extra space and same applicable below.
REG_BIT can be used. Please refer kernel doc added as header of this file.

Regards,
Animesh
> +#define  EXITLINE_MASK		(0x1fff)
> +#define  EXITLINE_SHIFT		0
> +
>   /*
>    * HSW+ eDP PSR registers
>    *
> @@ -10114,6 +10120,8 @@ enum skl_power_gate {
>   /* GEN9 DC */
>   #define DC_STATE_EN			_MMIO(0x45504)
>   #define  DC_STATE_DISABLE		0
> +#define  DC_STATE_EN_DC3CO		(1 << 30)
> +#define  DC_STATE_DC3CO_STATUS		(1 << 29)
>   #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>   #define  DC_STATE_EN_DC9		(1 << 3)
>   #define  DC_STATE_EN_UPTO_DC6		(2 << 0)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..273a4ed8b3e9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4135,6 +4135,7 @@  enum {
 #define _VTOTAL_A	0x6000c
 #define _VBLANK_A	0x60010
 #define _VSYNC_A	0x60014
+#define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
@@ -4181,11 +4182,16 @@  enum {
 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define  EXITLINE_ENABLE	(1 << 31)
+#define  EXITLINE_MASK		(0x1fff)
+#define  EXITLINE_SHIFT		0
+
 /*
  * HSW+ eDP PSR registers
  *
@@ -10114,6 +10120,8 @@  enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
+#define  DC_STATE_EN_DC3CO		(1 << 30)
+#define  DC_STATE_DC3CO_STATUS		(1 << 29)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)