From patchwork Sat Sep 7 17:14:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B40C1395 for ; Sat, 7 Sep 2019 17:21:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52805208C3 for ; Sat, 7 Sep 2019 17:21:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52805208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C34D89DB2; Sat, 7 Sep 2019 17:21:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id F219389DB4 for ; Sat, 7 Sep 2019 17:21:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111429" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:31 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:37 +0530 Message-Id: <20190907171443.16181-2-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 1/7] drm/i915/tgl: Add DC3CO required register and bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Adding following definition to i915_reg.h 1. DC_STATE_EN register DC3CO bit fields and masks. 2. Transcoder EXITLINE register and its bit fields and mask. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 006cffd56be2..273a4ed8b3e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4135,6 +4135,7 @@ enum { #define _VTOTAL_A 0x6000c #define _VBLANK_A 0x60010 #define _VSYNC_A 0x60014 +#define _EXITLINE_A 0x60018 #define _PIPEASRC 0x6001c #define _BCLRPAT_A 0x60020 #define _VSYNCSHIFT_A 0x60028 @@ -4181,11 +4182,16 @@ enum { #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) +#define EXITLINE_ENABLE (1 << 31) +#define EXITLINE_MASK (0x1fff) +#define EXITLINE_SHIFT 0 + /* * HSW+ eDP PSR registers * @@ -10114,6 +10120,8 @@ enum skl_power_gate { /* GEN9 DC */ #define DC_STATE_EN _MMIO(0x45504) #define DC_STATE_DISABLE 0 +#define DC_STATE_EN_DC3CO (1 << 30) +#define DC_STATE_DC3CO_STATUS (1 << 29) #define DC_STATE_EN_UPTO_DC5 (1 << 0) #define DC_STATE_EN_DC9 (1 << 3) #define DC_STATE_EN_UPTO_DC6 (2 << 0)