From patchwork Sat Sep 7 17:14:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FA981395 for ; Sat, 7 Sep 2019 17:21:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65F0A208C3 for ; Sat, 7 Sep 2019 17:21:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65F0A208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A1C889DBC; Sat, 7 Sep 2019 17:21:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2CFA589DBF for ; Sat, 7 Sep 2019 17:21:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111451" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:42 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:41 +0530 Message-Id: <20190907171443.16181-6-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 5/7] drm/i915/tgl: DC3CO PSR2 helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add dc3co helper functions to enable/disable psr2 deep sleep. Adhere B.Specs by disallow DC3CO state before PSR2 exit. Enable PSR2 exitline event and program the desired scanlines to exit DC3CO in intel_psr_enable function at modeset path. Disable the DC3CO exitline in order to maintian consistent pipe config state in encoder disable path. v1: moved calling of tgl_enable_psr2_transcoder_exitline() to intel_psr_enable(). [Imre] Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: José Roberto de Souza Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b3c7eef53bf3..95b12946c72a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -534,6 +534,48 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) return trans == TRANSCODER_EDP; } +static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, + u32 idle_frames) +{ + u32 val; + + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; + val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); + val &= ~EDP_PSR2_IDLE_FRAME_MASK; + val |= idle_frames; + I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); +} + +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv) +{ + int idle_frames = 0; + + psr2_program_idle_frames(dev_priv, idle_frames); +} + +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv) +{ + int idle_frames; + + /* + * Let's use 6 as the minimum to cover all known cases including the + * off-by-one issue that HW has in some cases. + */ + idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); + psr2_program_idle_frames(dev_priv, idle_frames); +} + +static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) +{ + if (!IS_TIGERLAKE(dev_priv)) + return; + + cancel_delayed_work(&dev_priv->csr.idle_work); + /* Before PSR2 exit disallow dc3co*/ + tgl_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6, true); +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -799,6 +841,10 @@ void intel_psr_enable(struct intel_dp *intel_dp, WARN_ON(dev_priv->drrs.dp); + /* Enable PSR2 transcoder exit line */ + if (crtc_state->has_psr2) + tgl_enable_psr2_transcoder_exitline(crtc_state); + mutex_lock(&dev_priv->psr.lock); if (!psr_global_enabled(dev_priv->psr.debug)) { @@ -829,6 +875,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) } if (dev_priv->psr.psr2_enabled) { + tgl_disallow_dc3co_on_psr2_exit(dev_priv); val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); WARN_ON(!(val & EDP_PSR2_ENABLE)); val &= ~EDP_PSR2_ENABLE; @@ -895,6 +942,10 @@ void intel_psr_disable(struct intel_dp *intel_dp, if (WARN_ON(!CAN_PSR(dev_priv))) return; + /* Disable PSR2 transcoder exit line */ + if (old_crtc_state->has_psr2) + tgl_disable_psr2_transcoder_exitline(old_crtc_state); + mutex_lock(&dev_priv->psr.lock); intel_psr_disable_locked(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 46e4de8b8cd5..75a9862f36fd 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -35,5 +35,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp); int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, u32 *out_value); bool intel_psr_enabled(struct intel_dp *intel_dp); +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv); +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv); #endif /* __INTEL_PSR_H__ */