| Message ID | 20190910190756.31432-2-jae.hyun.yoo@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: aspeed: refine mode detection flow | expand |
On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote: > This commit refines hsync/vsync polarity setting logic by making > also clearing register bits possible based on probed sync state > accordingly. That was tough to parse, but I think I understand. Trying to rephrase: Enable clearing of hsync/vsync plarity bits based on probed sync state. What was the issue that drove the change? Do you know why it was done the way it was prior to this patch? Andrew
Hi Andrew, On 9/11/2019 10:33 PM, Andrew Jeffery wrote: > On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote: >> This commit refines hsync/vsync polarity setting logic by making >> also clearing register bits possible based on probed sync state >> accordingly. > > That was tough to parse, but I think I understand. Trying to rephrase: > > Enable clearing of hsync/vsync plarity bits based on probed sync state. Correct. > What was the issue that drove the change? Do you know why it was done > the way it was prior to this patch? Because this driver detects weird resolutions sometimes. Investigated that it uses aspeed_video_update(video, VE_CTRL, 0, ctrl); so only setting of polarity bits is available. Means that clearing of the bits isn't available so it can't set back the polarities to normal. To fix the issue, this patch makes it use aspeed_video_write(video, VE_CTRL, ctrl); instead of above one with adding bit masking code changes. Thanks, Jae
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c index eb12f3793062..8f77079da55a 100644 --- a/drivers/media/platform/aspeed-video.c +++ b/drivers/media/platform/aspeed-video.c @@ -614,7 +614,7 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) int i; int hsync_counter = 0; int vsync_counter = 0; - u32 sts; + u32 sts, ctrl; for (i = 0; i < NUM_POLARITY_CHECKS; ++i) { sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS); @@ -629,30 +629,29 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) hsync_counter++; } - if (hsync_counter < 0 || vsync_counter < 0) { - u32 ctrl = 0; + ctrl = aspeed_video_read(video, VE_CTRL); - if (hsync_counter < 0) { - ctrl = VE_CTRL_HSYNC_POL; - video->detected_timings.polarities &= - ~V4L2_DV_HSYNC_POS_POL; - } else { - video->detected_timings.polarities |= - V4L2_DV_HSYNC_POS_POL; - } - - if (vsync_counter < 0) { - ctrl = VE_CTRL_VSYNC_POL; - video->detected_timings.polarities &= - ~V4L2_DV_VSYNC_POS_POL; - } else { - video->detected_timings.polarities |= - V4L2_DV_VSYNC_POS_POL; - } + if (hsync_counter < 0) { + ctrl |= VE_CTRL_HSYNC_POL; + video->detected_timings.polarities &= + ~V4L2_DV_HSYNC_POS_POL; + } else { + ctrl &= ~VE_CTRL_HSYNC_POL; + video->detected_timings.polarities |= + V4L2_DV_HSYNC_POS_POL; + } - if (ctrl) - aspeed_video_update(video, VE_CTRL, 0, ctrl); + if (vsync_counter < 0) { + ctrl |= VE_CTRL_VSYNC_POL; + video->detected_timings.polarities &= + ~V4L2_DV_VSYNC_POS_POL; + } else { + ctrl &= ~VE_CTRL_VSYNC_POL; + video->detected_timings.polarities |= + V4L2_DV_VSYNC_POS_POL; } + + aspeed_video_write(video, VE_CTRL, ctrl); } static bool aspeed_video_alloc_buf(struct aspeed_video *video,
This commit refines hsync/vsync polarity setting logic by making also clearing register bits possible based on probed sync state accordingly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> --- drivers/media/platform/aspeed-video.c | 43 +++++++++++++-------------- 1 file changed, 21 insertions(+), 22 deletions(-)