diff mbox series

[3/4] drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+

Message ID 20190911133129.27466-3-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk | expand

Commit Message

Ville Syrjälä Sept. 11, 2019, 1:31 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
copy.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++--------------------
 1 file changed, 2 insertions(+), 35 deletions(-)

Comments

Matt Roper Sept. 11, 2019, 3:03 p.m. UTC | #1 
On Wed, Sep 11, 2019 at 04:31:28PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
> copy.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++--------------------
>  1 file changed, 2 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f59a6f775177..f5a99eb77efa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2227,39 +2227,6 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
>  	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
> -	state->cdclk.logical.vco = vco;
> -	state->cdclk.logical.cdclk = cdclk;
> -	state->cdclk.logical.voltage_level =
> -		max(cnl_calc_voltage_level(cdclk),
> -		    cnl_compute_min_voltage_level(state));
> -
> -	if (!state->active_pipes) {
> -		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> -		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> -		state->cdclk.actual.vco = vco;
> -		state->cdclk.actual.cdclk = cdclk;
> -		state->cdclk.actual.voltage_level =
> -			cnl_calc_voltage_level(cdclk);
> -	} else {
> -		state->cdclk.actual = state->cdclk.logical;
> -	}
> -
> -	return 0;
> -}
> -
> -static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	int min_cdclk, cdclk, vco;
> -
> -	min_cdclk = intel_compute_min_cdclk(state);
> -	if (min_cdclk < 0)
> -		return min_cdclk;
> -
> -	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> -	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
>  	state->cdclk.logical.voltage_level =
> @@ -2499,12 +2466,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ELKHARTLAKE(dev_priv)) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (INTEL_GEN(dev_priv) >= 11) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f59a6f775177..f5a99eb77efa 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2227,39 +2227,6 @@  static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
 	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
-	state->cdclk.logical.vco = vco;
-	state->cdclk.logical.cdclk = cdclk;
-	state->cdclk.logical.voltage_level =
-		max(cnl_calc_voltage_level(cdclk),
-		    cnl_compute_min_voltage_level(state));
-
-	if (!state->active_pipes) {
-		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
-		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
-		state->cdclk.actual.vco = vco;
-		state->cdclk.actual.cdclk = cdclk;
-		state->cdclk.actual.voltage_level =
-			cnl_calc_voltage_level(cdclk);
-	} else {
-		state->cdclk.actual = state->cdclk.logical;
-	}
-
-	return 0;
-}
-
-static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	int min_cdclk, cdclk, vco;
-
-	min_cdclk = intel_compute_min_cdclk(state);
-	if (min_cdclk < 0)
-		return min_cdclk;
-
-	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
-	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
 	state->cdclk.logical.voltage_level =
@@ -2499,12 +2466,12 @@  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ELKHARTLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {