From patchwork Thu Sep 12 07:22:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Gao X-Patchwork-Id: 11142477 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 830F11599 for ; Thu, 12 Sep 2019 07:20:34 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6948421479 for ; Thu, 12 Sep 2019 07:20:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6948421479 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1i8JOO-0002AM-K5; Thu, 12 Sep 2019 07:19:48 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1i8JON-000290-7S for xen-devel@lists.xenproject.org; Thu, 12 Sep 2019 07:19:47 +0000 X-Inumbo-ID: a27761e6-d52d-11e9-83e3-12813bfff9fa Received: from mga01.intel.com (unknown [192.55.52.88]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id a27761e6-d52d-11e9-83e3-12813bfff9fa; Thu, 12 Sep 2019 07:19:18 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Sep 2019 00:19:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,492,1559545200"; d="scan'208";a="189906404" Received: from gao-cwp.sh.intel.com ([10.239.159.26]) by orsmga006.jf.intel.com with ESMTP; 12 Sep 2019 00:19:16 -0700 From: Chao Gao To: xen-devel@lists.xenproject.org Date: Thu, 12 Sep 2019 15:22:29 +0800 Message-Id: <1568272949-1086-17-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1568272949-1086-1-git-send-email-chao.gao@intel.com> References: <1568272949-1086-1-git-send-email-chao.gao@intel.com> Subject: [Xen-devel] [PATCH v10 16/16] microcode/intel: writeback and invalidate cache conditionally X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Sergey Dyasli , Ashok Raj , Wei Liu , Andrew Cooper , Jan Beulich , Chao Gao , =?utf-8?q?R?= =?utf-8?q?oger_Pau_Monn=C3=A9?= MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" It is needed to mitigate some issues on this specific Broadwell CPU. Signed-off-by: Chao Gao --- xen/arch/x86/microcode_intel.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index bcef668..4e5e7f9 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -305,6 +305,31 @@ static bool is_blacklisted(void) return false; } +static void microcode_quirk(void) +{ + struct cpuinfo_x86 *c; + uint64_t llc_size; + + /* + * Don't refer to current_cpu_data, which isn't fully initialized + * before this stage. + */ + if ( system_state < SYS_STATE_smp_boot ) + return; + + c = ¤t_cpu_data; + llc_size = c->x86_cache_size * 1024ULL; + do_div(llc_size, c->x86_max_cores); + + /* + * To mitigate some issues on this specific Broadwell CPU, writeback and + * invalidate cache regardless of ucode revision. + */ + if ( c->x86 == 6 && c->x86_model == 0x4F && c->x86_mask == 0x1 && + llc_size > 2621440 ) + wbinvd(); +} + static int apply_microcode(const struct microcode_patch *patch) { uint64_t msr_content; @@ -323,6 +348,8 @@ static int apply_microcode(const struct microcode_patch *patch) BUG_ON(local_irq_is_enabled()); + microcode_quirk(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);