From patchwork Thu Sep 12 11:39:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11142879 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56FA21599 for ; Thu, 12 Sep 2019 11:39:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 35DAF20CC7 for ; Thu, 12 Sep 2019 11:39:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ybZlpbY6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731334AbfILLjl (ORCPT ); Thu, 12 Sep 2019 07:39:41 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54840 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730680AbfILLjl (ORCPT ); Thu, 12 Sep 2019 07:39:41 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CBdPbD125282; Thu, 12 Sep 2019 06:39:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568288365; bh=oQxDXztiLLCcC6n0PYFQficOreSIf5synk8KoO4IaU0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ybZlpbY6DvSrOtRNXOFwn8qVbTWd7Hci76yIEzhPOeHdapm5nBBK7F/PHXkfWrll2 Lh6utvPhf2uUNTGzAiBiQ3J74+Ce5yKNmXyYak9W/n2fWJEPusTCqz2Kr0/YguHqwD WDl9S9sMWcB5Y794CWPt9hRwxjsWs5uXmTs0MeWQ= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8CBdPhD050703 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Sep 2019 06:39:25 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 06:39:25 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 06:39:25 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CBdKcq120606; Thu, 12 Sep 2019 06:39:23 -0500 From: Tero Kristo To: , , , , , CC: , Subject: [PATCHv5 01/10] dt-bindings: omap: add new binding for PRM instances Date: Thu, 12 Sep 2019 14:39:07 +0300 Message-ID: <20190912113916.20093-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912113916.20093-1-t-kristo@ti.com> References: <20190912113916.20093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo Reviewed-by: Rob Herring --- v5: - dropped the clocks property as the dependency towards clocks was removed - changed the name of the node to be power-controller .../devicetree/bindings/arm/omap/prm-inst.txt | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..942f7aac3b00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,27 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must be one of: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. + +Example: + +prm_dsp2: power-controller@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; +};