| Message ID | 1568364608-46548-1-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 8438bfda9d76815707a7823ab91a944eea6d6266 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [1/2] arm64: dts: renesas: r8a774c0: Create thermal zone to support IPA | expand |
On Fri, Sep 13, 2019 at 09:50:07AM +0100, Biju Das wrote: > Setup a thermal zone driven by SoC temperature sensor. > Create passive trip points and bind them to CPUFreq cooling > device that supports power extension. > > Based on the work done by Dien Pham <dien.pham.ry@renesas.com> > and others for r8a77990 SoC. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> > --- > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > index a1c2de9..764df4c 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > @@ -73,6 +73,7 @@ > compatible = "arm,cortex-a53"; > reg = <0>; > device_type = "cpu"; > + #cooling-cells = <2>; > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > @@ -1905,18 +1906,30 @@ > thermal-zones { > cpu-thermal { > polling-delay-passive = <250>; > - polling-delay = <1000>; > - thermal-sensors = <&thermal>; > + polling-delay = <0>; > + thermal-sensors = <&thermal 0>; > + sustainable-power = <717>; > > cooling-maps { > + map0 { > + trip = <&target>; > + cooling-device = <&a53_0 0 2>; > + contribution = <1024>; > + }; > }; > > trips { > - cpu-crit { > + sensor1_crit: sensor1-crit { > temperature = <120000>; > hysteresis = <2000>; > type = "critical"; > }; > + > + target: trip-point1 { > + temperature = <100000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > }; > }; > }; > -- > 2.7.4 >
On Fri, Sep 13, 2019 at 10:57 AM Biju Das <biju.das@bp.renesas.com> wrote: > Setup a thermal zone driven by SoC temperature sensor. > Create passive trip points and bind them to CPUFreq cooling > device that supports power extension. > > Based on the work done by Dien Pham <dien.pham.ry@renesas.com> > and others for r8a77990 SoC. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.5. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index a1c2de9..764df4c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -73,6 +73,7 @@ compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; @@ -1905,18 +1906,30 @@ thermal-zones { cpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; + polling-delay = <0>; + thermal-sensors = <&thermal 0>; + sustainable-power = <717>; cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; }; trips { - cpu-crit { + sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; + + target: trip-point1 { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; }; }; };
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham <dien.pham.ry@renesas.com> and others for r8a77990 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)