drm/i915/tgl: Limit ourselves to just rcs0
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Message ID 20190913111443.29244-1-chris@chris-wilson.co.uk
State New
Headers show
Series
  • drm/i915/tgl: Limit ourselves to just rcs0
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Commit Message

Chris Wilson Sept. 13, 2019, 11:14 a.m. UTC
More pruning away of features until we have a stable system and a basis
for debugging what's missing.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Mika Kuoppala Sept. 13, 2019, 12:25 p.m. UTC | #1
Chris Wilson <chris@chris-wilson.co.uk> writes:

> More pruning away of features until we have a stable system and a basis
> for debugging what's missing.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9236fccb3a83..ee9a7959204c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -799,6 +799,7 @@ static const struct intel_device_info intel_tigerlake_12_info = {
>  		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>  	.has_rc6 = false, /* XXX disabled for debugging */
>  	.has_logical_ring_preemption = false, /* XXX disabled for debugging */
> +	.engine_mask = BIT(RCS0), /* XXX reduced for debugging */

Yeah, that will do.

I have tried to find a pairing that works. It is either gttfill or
gem_sync depending on pair.

We yearn for coverage so,
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  };
>  
>  #undef GEN
> -- 
> 2.23.0

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9236fccb3a83..ee9a7959204c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -799,6 +799,7 @@  static const struct intel_device_info intel_tigerlake_12_info = {
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.has_rc6 = false, /* XXX disabled for debugging */
 	.has_logical_ring_preemption = false, /* XXX disabled for debugging */
+	.engine_mask = BIT(RCS0), /* XXX reduced for debugging */
 };
 
 #undef GEN