@@ -2667,6 +2667,65 @@ static bool tgl_dkl_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
return false;
}
+struct tgl_dp_frequencies {
+ u32 hsclkctl;
+ u32 coreclkctl1;
+ u32 ssc_reg;
+};
+
+static void
+tgl_dkl_pll_overwrite_with_hardcoded_values(int clock_khz,
+ struct intel_dpll_hw_state *state,
+ bool is_dp)
+{
+ const struct tgl_dp_frequencies tgl_dkl_pll_dp_frequencies[] = {
+ { 0x011D, 0x10080510, 0x401320ff }, /* 8p1 */
+ { 0x121D, 0x10080510, 0x401320ff }, /* 5p4 */
+ { 0x521D, 0x10080A12, 0x401320ff }, /* 2p7 */
+ { 0x621D, 0x10080A12, 0x401320ff }, /* 1p62 */
+ };
+ int i;
+
+ if (!is_dp) {
+ /* No hardcoded values for HDMI */
+ MISSING_CASE(!is_dp);
+ return;
+ }
+
+ switch (clock_khz) {
+ case 810000:
+ i = 0;
+ break;
+ case 540000:
+ i = 1;
+ break;
+ case 270000:
+ i = 2;
+ break;
+ case 162000:
+ i = 3;
+ break;
+ default:
+ MISSING_CASE(clock_khz);
+ return;
+ }
+
+ state->mg_clktop2_coreclkctl1 = tgl_dkl_pll_dp_frequencies[i].coreclkctl1;
+ state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+ state->mg_clktop2_hsclkctl = tgl_dkl_pll_dp_frequencies[i].hsclkctl;
+ state->mg_clktop2_hsclkctl &= (MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+
+ state->mg_pll_ssc = tgl_dkl_pll_dp_frequencies[i].ssc_reg;
+ state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+ DKL_PLL_SSC_STEP_LEN_MASK |
+ DKL_PLL_SSC_STEP_NUM_MASK |
+ DKL_PLL_SSC_EN);
+}
+
/*
* The specification for this function uses real numbers, so the math had to be
* adapted to integer-only calculation, that's why it looks so different.
@@ -2798,6 +2857,13 @@ static bool tgl_calc_dkl_pll_state(struct intel_crtc_state *crtc_state,
DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
+ /*
+ * BSpec PLL calculations are not validated/ready yet, so for now lets
+ * fallback to the hardcoded table.
+ */
+ tgl_dkl_pll_overwrite_with_hardcoded_values(symbol_frequency,
+ pll_state, is_dp);
+
return true;
}