[13/14] drm/i915/tgl: Use dkl pll hardcoded values
diff mbox series

Message ID 20190913223251.354877-14-jose.souza@intel.com
State New
Headers show
Series
  • TGL TC enabling
Related show

Commit Message

Souza, Jose Sept. 13, 2019, 10:32 p.m. UTC
From: "Taylor, Clinton A" <clinton.a.taylor@intel.com>

BSpec PLL calculation are not validated/ready yet, so for now it is
providing a table with hardcoded values to all DP link rates.
So for now lets override the calculated values with the hardcoded
ones.

With this hardcoded values the port clock calculation for 5.4Ghz
don't match but this is a minor error that we can live for now.

Bspec: 49204

Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 25be6229b122..5b568dd57a5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2667,6 +2667,65 @@  static bool tgl_dkl_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 	return false;
 }
 
+struct tgl_dp_frequencies {
+	u32 hsclkctl;
+	u32 coreclkctl1;
+	u32 ssc_reg;
+};
+
+static void
+tgl_dkl_pll_overwrite_with_hardcoded_values(int clock_khz,
+					    struct intel_dpll_hw_state *state,
+					    bool is_dp)
+{
+	const struct tgl_dp_frequencies tgl_dkl_pll_dp_frequencies[] = {
+		{ 0x011D, 0x10080510, 0x401320ff },	/* 8p1 */
+		{ 0x121D, 0x10080510, 0x401320ff },	/* 5p4 */
+		{ 0x521D, 0x10080A12, 0x401320ff },	/* 2p7 */
+		{ 0x621D, 0x10080A12, 0x401320ff },	/* 1p62 */
+	};
+	int i;
+
+	if (!is_dp) {
+		/* No hardcoded values for HDMI */
+		MISSING_CASE(!is_dp);
+		return;
+	}
+
+	switch (clock_khz) {
+	case 810000:
+		i = 0;
+		break;
+	case 540000:
+		i = 1;
+		break;
+	case 270000:
+		i = 2;
+		break;
+	case 162000:
+		i = 3;
+		break;
+	default:
+		MISSING_CASE(clock_khz);
+		return;
+	}
+
+	state->mg_clktop2_coreclkctl1 = tgl_dkl_pll_dp_frequencies[i].coreclkctl1;
+	state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+	state->mg_clktop2_hsclkctl = tgl_dkl_pll_dp_frequencies[i].hsclkctl;
+	state->mg_clktop2_hsclkctl &= (MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+				       MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+				       MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+				       MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+
+	state->mg_pll_ssc = tgl_dkl_pll_dp_frequencies[i].ssc_reg;
+	state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+			      DKL_PLL_SSC_STEP_LEN_MASK |
+			      DKL_PLL_SSC_STEP_NUM_MASK |
+			      DKL_PLL_SSC_EN);
+}
+
 /*
  * The specification for this function uses real numbers, so the math had to be
  * adapted to integer-only calculation, that's why it looks so different.
@@ -2798,6 +2857,13 @@  static bool tgl_calc_dkl_pll_state(struct intel_crtc_state *crtc_state,
 			DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
 			DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
 
+	/*
+	 * BSpec PLL calculations are not validated/ready yet, so for now lets
+	 * fallback to the hardcoded table.
+	 */
+	tgl_dkl_pll_overwrite_with_hardcoded_values(symbol_frequency,
+						    pll_state, is_dp);
+
 	return true;
 }