diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 81792a04e0aa..dd3db5844bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -586,6 +586,25 @@ static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 	{ 0x0, 0x00, 0x00 },	/* 3              0   */
 };
 
+struct tgl_dkl_phy_ddi_buf_trans {
+	u32 dkl_vswing_control;
+	u32 dkl_preshoot_control;
+	u32 dkl_de_emphasis_control;
+};
+
+static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
+	{ 0x7, 0x0, 0x00 },	/* 0     0   400mV  0 dB   */
+	{ 0x5, 0x0, 0x03 },	/* 0     1   400mV  3.5 dB */
+	{ 0x2, 0x0, 0x0b },	/* 0     2   400mV  6 dB   */
+	{ 0x0, 0x0, 0x19 },	/* 0     3   400mV  9.5 dB */
+	{ 0x5, 0x0, 0x00 },	/* 1     0   600mV  0 dB   */
+	{ 0x2, 0x0, 0x03 },	/* 1     1   600mV  3.5 dB */
+	{ 0x0, 0x0, 0x14 },	/* 1     2   600mV  6 dB   */
+	{ 0x2, 0x0, 0x00 },	/* 2     0   800mV  0 dB   */
+	{ 0x0, 0x0, 0x0B },	/* 2     1   800mV  3.5 dB */
+	{ 0x0, 0x0, 0x00 },	/* 3     0  1200mV  0 dB    HDMI Default */
+};
+
 static const struct ddi_buf_trans *
 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
@@ -873,11 +892,15 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_phy_is_combo(dev_priv, phy))
+		if (intel_phy_is_combo(dev_priv, phy)) {
 			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
-		else
-			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+		} else {
+			if (INTEL_GEN(dev_priv) >= 12)
+				n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+			else
+				n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+		}
 		default_entry = n_entries - 1;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
@@ -2308,11 +2331,15 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	int n_entries;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_phy_is_combo(dev_priv, phy))
+		if (intel_phy_is_combo(dev_priv, phy)) {
 			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
-		else
-			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+		} else {
+			if (INTEL_GEN(dev_priv) >= 12)
+				n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+			else
+				n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+		}
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		if (encoder->type == INTEL_OUTPUT_EDP)
 			cnl_get_buf_trans_edp(dev_priv, &n_entries);
@@ -2749,6 +2776,66 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
 }
 
+static void
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
+				u32 level)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
+	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
+	u32 n_entries, val, ln;
+
+	n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+	ddi_translations = tgl_dkl_phy_ddi_translations;
+
+	if (level > n_entries)
+		level = n_entries - 1;
+
+	/*
+	 * All registers programmed here use HIP_INDEX_REG 0 or 1
+	 */
+	for (ln = 0; ln < 2; ln++) {
+		I915_WRITE(HIP_INDEX_REG(tc_port), ln);
+
+		/* All the registers are RMW */
+		val = I915_READ(DKL_TX_DPCNTL0(tc_port));
+		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
+			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			 DKL_TX_VSWING_CONTROL_MASK);
+		val |= DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
+		val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
+		val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
+		I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
+
+		val = I915_READ(DKL_TX_DPCNTL1(tc_port));
+		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
+			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			 DKL_TX_VSWING_CONTROL_MASK);
+		val |= DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
+		val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
+		val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
+		I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
+
+		val = I915_READ(DKL_TX_DPCNTL2(tc_port));
+		val &= ~DKL_TX_DP20BITMODE;
+		I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
+	}
+}
+
+static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
+				    int link_clock,
+				    u32 level,
+				    enum intel_output_type type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	if (intel_phy_is_combo(dev_priv, phy))
+		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+	else
+		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
+}
+
 static u32 translate_signal_level(int signal_levels)
 {
 	int i;
@@ -2780,7 +2867,10 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dport->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
+					level, encoder->type);
+	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
 					level, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -3027,6 +3117,34 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	}
 }
 
+static void
+tgl_phy_clock_gating(struct intel_digital_port *dig_port, bool enable)
+{
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum port port = dig_port->base.port;
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+	u32 val, regs;
+	int ln;
+
+	if (tc_port == PORT_TC_NONE)
+		return;
+
+	regs = DKL_DP_MODE_CFG_TR2PWR_GATING | DKL_DP_MODE_CFG_TRPWR_GATING |
+	       DKL_DP_MODE_CFG_CLNPWR_GATING | DKL_DP_MODE_CFG_DIGPWR_GATING |
+	       DKL_DP_MODE_CFG_GAONPWR_GATING;
+
+	for (ln = 0; ln < 2; ln++) {
+		I915_WRITE(HIP_INDEX_REG(tc_port), ln);
+
+		val = I915_READ(DKL_DP_MODE(tc_port));
+		if (enable)
+			val |= regs;
+		else
+			val &= ~regs;
+		I915_WRITE(DKL_DP_MODE(tc_port), val);
+	}
+}
+
 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
@@ -3153,6 +3271,95 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
 	I915_WRITE(MG_DP_MODE(1, port), ln1);
 }
 
+static void tgl_program_dkl_dp_mode(struct intel_digital_port *intel_dig_port)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
+	enum port port = intel_dig_port->base.port;
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+	u32 ln0, ln1, lane_mask, pin_mask;
+	int num_lanes;
+
+	if (tc_port == PORT_TC_NONE ||
+	    intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
+		return;
+
+	I915_WRITE(HIP_INDEX_REG(tc_port), 0x0);
+	ln0 = I915_READ(DKL_DP_MODE(tc_port));
+	I915_WRITE(HIP_INDEX_REG(tc_port), 0x1);
+	ln1 = I915_READ(DKL_DP_MODE(tc_port));
+
+	num_lanes = intel_dig_port->dp.lane_count;
+
+	switch (intel_dig_port->tc_mode) {
+	case TC_PORT_DP_ALT:
+		ln0 &= ~(DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X1_MODE);
+		ln1 &= ~(DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X2_MODE);
+
+		lane_mask = intel_tc_port_get_lane_mask(intel_dig_port); /* DPX4TXLATC */
+		pin_mask = intel_tc_port_get_pin_assignment_mask(intel_dig_port); /* DPPATC */
+
+		switch (pin_mask) {
+		case 0x0:
+			if (num_lanes == 1) {
+				ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE;
+			} else {
+				ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+			}
+			break;
+		case 0x1:
+			if (num_lanes == 4) {
+				ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+			}
+			break;
+		case 0x2:
+			if (num_lanes == 2) {
+				ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+			}
+			break;
+		case 0x3:
+		case 0x5:
+			if (num_lanes == 1) {
+				ln0 |= DKL_DP_MODE_CFG_DP_X1_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE;
+			} else {
+				ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+			}
+			break;
+		case 0x4:
+		case 0x6:
+			if (num_lanes == 1) {
+				ln0 |= DKL_DP_MODE_CFG_DP_X1_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE;
+			} else {
+				ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+				ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
+			}
+			break;
+		default:
+			MISSING_CASE(lane_mask);
+		}
+		break;
+
+	case TC_PORT_LEGACY:
+		ln0 |= DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X2_MODE;
+		ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X2_MODE;
+		break;
+
+	default:
+		MISSING_CASE(intel_dig_port->tc_mode);
+		return;
+	}
+
+	I915_WRITE(HIP_INDEX_REG(tc_port), 0x0);
+	I915_WRITE(DKL_DP_MODE(tc_port), ln0);
+	I915_WRITE(HIP_INDEX_REG(tc_port), 0x1);
+	I915_WRITE(DKL_DP_MODE(tc_port), ln1);
+}
+
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
 					const struct intel_crtc_state *crtc_state)
 {
@@ -3239,7 +3446,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 					dig_port->ddi_io_power_domain);
 
 	/* 6. */
-	icl_program_mg_dp_mode(dig_port);
+	tgl_program_dkl_dp_mode(dig_port);
 
 	/*
 	 * 7.a - Steps in this function should only be executed over MST
@@ -3252,10 +3459,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	intel_ddi_config_transcoder_func(crtc_state);
 
 	/* 7.d */
-	icl_disable_phy_clock_gating(dig_port);
+	tgl_phy_clock_gating(dig_port, false);
 
 	/* 7.e */
-	icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
+	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
 				encoder->type);
 
 	/* 7.f */
@@ -3287,6 +3494,15 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	/* 7.k */
 	intel_dp_stop_link_train(intel_dp);
 
+	/*
+	 * TODO: enable clock gating
+	 *
+	 * It is not written in DP enabling sequence but "PHY Clockgating
+	 * programming" states that clock gating should be enabled after the
+	 * link training but doing so causes all the following trainings to fail
+	 * so not enabling it for.
+	 */
+
 	/* 7.l */
 	intel_ddi_enable_fec(encoder, crtc_state);
 	intel_dsc_enable(encoder, crtc_state);
@@ -3392,7 +3608,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
 
 	icl_program_mg_dp_mode(dig_port);
-	icl_disable_phy_clock_gating(dig_port);
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_phy_clock_gating(dig_port, false);
+	else
+		icl_disable_phy_clock_gating(dig_port);
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
@@ -3404,7 +3623,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	else
 		intel_prepare_hdmi_ddi_buffers(encoder, level);
 
-	icl_enable_phy_clock_gating(dig_port);
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_phy_clock_gating(dig_port, true);
+	else
+		icl_enable_phy_clock_gating(dig_port);
 
 	if (IS_GEN9_BC(dev_priv))
 		skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
