[11/14] drm/i915/tgl: Check the UC health of tc controllers after power on
diff mbox series

Message ID 20190913223251.354877-12-jose.souza@intel.com
State New
Headers show
Series
  • TGL TC enabling
Related show

Commit Message

Souza, Jose Sept. 13, 2019, 10:32 p.m. UTC
New step added for TGL, requiring for us to check the TC
microcontroller health after power on TC aux.

BSpec: 49294

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../gpu/drm/i915/display/intel_display_power.c   | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce88a27229ef..14e4ac6ee54d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -562,6 +562,8 @@  static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
 
 #endif
 
+#define TGL_AUX_PW_TO_TC_PORT(pw_idx)	((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
+
 static void
 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 				 struct i915_power_well *power_well)
@@ -578,6 +580,20 @@  icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 	I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
 
 	hsw_power_well_enable(dev_priv, power_well);
+
+	if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) {
+		enum tc_port tc_port;
+
+		tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
+		val = I915_READ(HIP_INDEX_REG(tc_port));
+		val &= ~HIP_INDEX_MASK(tc_port);
+		val |= HIP_INDEX_INDEX_VAL(tc_port, 0x2);
+		I915_WRITE(HIP_INDEX_REG(tc_port), val);
+
+		if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
+					  DKL_CMN_UC_DW27_UC_HEALTH, 1))
+			DRM_WARN("Timeout waiting TC uC health\n");
+	}
 }
 
 static void