clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
diff mbox series

Message ID 20190914135100.327412-1-jernej.skrabec@siol.net
State New
Headers show
Series
  • clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
Related show

Commit Message

Jernej Skrabec Sept. 14, 2019, 1:51 p.m. UTC
Audio devices needs exact clock rates in order to correctly reproduce
the sound. Until now, only integer factors were used to configure H6
audio PLL which resulted in inexact rates. Fix that by adding support
for fractional factors using sigma-delta modulation look-up table. It
contains values for two most commonly used audio base frequencies.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

Comments

Chen-Yu Tsai Sept. 17, 2019, 6:54 a.m. UTC | #1
On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec <jernej.skrabec@siol.net> wrote:
>
> Audio devices needs exact clock rates in order to correctly reproduce
> the sound. Until now, only integer factors were used to configure H6
> audio PLL which resulted in inexact rates. Fix that by adding support
> for fractional factors using sigma-delta modulation look-up table. It
> contains values for two most commonly used audio base frequencies.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
>  1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> index d89353a3cdec..ed6338d74474 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> @@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
>   * hardcode it to match with the clock names.
>   */
>  #define SUN50I_H6_PLL_AUDIO_REG                0x078
> +
> +static struct ccu_sdm_setting pll_audio_sdm_table[] = {
> +       { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
> +       { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
> +};
> +
>  static struct ccu_nm pll_audio_base_clk = {
>         .enable         = BIT(31),
>         .lock           = BIT(28),
>         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
> +       .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table,
> +                                        BIT(24), 0x178, BIT(31)),
>         .common         = {
> +               .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
>                 .reg            = 0x078,
>                 .hw.init        = CLK_HW_INIT("pll-audio-base", "osc24M",
>                                               &ccu_nm_ops,
> @@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
>  };
>
>  /*
> - * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
> - * fixed post-divider 2.
> + * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
> + * rates can be set exactly in conjunction with sigma-delta modulation.
>   */
>  static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
>                             clk_parent_pll_audio,
> -                           8, 1, CLK_SET_RATE_PARENT);
> +                           24, 1, CLK_SET_RATE_PARENT);
>  static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
>                             clk_parent_pll_audio,
>                             4, 1, CLK_SET_RATE_PARENT);

You need to fix the factors for the other two outputs as well, since all
three are derived from pll-audio-base.

ChenYu

> @@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
>         }
>
>         /*
> -        * Force the post-divider of pll-audio to 8 and the output divider
> -        * of it to 1, to make the clock name represents the real frequency.
> +        * Force the post-divider of pll-audio to 12 and the output divider
> +        * of it to 2, so 24576000 and 22579200 rates can be set exactly.
>          */
>         val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
>         val &= ~(GENMASK(21, 16) | BIT(0));
> -       writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
> +       writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
>
>         /*
>          * First clock parent (osc32K) is unusable for CEC. But since there
> --
> 2.23.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190914135100.327412-1-jernej.skrabec%40siol.net.
Jernej Skrabec Sept. 18, 2019, 5:21 a.m. UTC | #2
Dne torek, 17. september 2019 ob 08:54:08 CEST je Chen-Yu Tsai napisal(a):
> On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec <jernej.skrabec@siol.net> 
wrote:
> > Audio devices needs exact clock rates in order to correctly reproduce
> > the sound. Until now, only integer factors were used to configure H6
> > audio PLL which resulted in inexact rates. Fix that by adding support
> > for fractional factors using sigma-delta modulation look-up table. It
> > contains values for two most commonly used audio base frequencies.
> > 
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> > 
> >  drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
> >  1 file changed, 15 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index d89353a3cdec..ed6338d74474
> > 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > @@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
> > 
> >   * hardcode it to match with the clock names.
> >   */
> >  
> >  #define SUN50I_H6_PLL_AUDIO_REG                0x078
> > 
> > +
> > +static struct ccu_sdm_setting pll_audio_sdm_table[] = {
> > +       { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
> > +       { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
> > +};
> > +
> > 
> >  static struct ccu_nm pll_audio_base_clk = {
> >  
> >         .enable         = BIT(31),
> >         .lock           = BIT(28),
> >         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> >         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
> > 
> > +       .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table,
> > +                                        BIT(24), 0x178, BIT(31)),
> > 
> >         .common         = {
> > 
> > +               .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
> > 
> >                 .reg            = 0x078,
> >                 .hw.init        = CLK_HW_INIT("pll-audio-base", "osc24M",
> >                 
> >                                               &ccu_nm_ops,
> > 
> > @@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] =
> > {> 
> >  };
> >  
> >  /*
> > 
> > - * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
> > - * fixed post-divider 2.
> > + * The divider of pll-audio is fixed to 24 for now, so 24576000 and
> > 22579200 + * rates can be set exactly in conjunction with sigma-delta
> > modulation.> 
> >   */
> >  
> >  static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
> >  
> >                             clk_parent_pll_audio,
> > 
> > -                           8, 1, CLK_SET_RATE_PARENT);
> > +                           24, 1, CLK_SET_RATE_PARENT);
> > 
> >  static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
> >  
> >                             clk_parent_pll_audio,
> >                             4, 1, CLK_SET_RATE_PARENT);
> 
> You need to fix the factors for the other two outputs as well, since all
> three are derived from pll-audio-base.

Fix how? pll-audio-2x and pll-audio-4x clocks have fixed divider in regards to 
pll-audio-base, while pll-audio has not. Unless you mean changing their name?

Best regards,
Jernej

> 
> ChenYu
> 
> > @@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct
> > platform_device *pdev)> 
> >         }
> >         
> >         /*
> > 
> > -        * Force the post-divider of pll-audio to 8 and the output divider
> > -        * of it to 1, to make the clock name represents the real
> > frequency. +        * Force the post-divider of pll-audio to 12 and the
> > output divider +        * of it to 2, so 24576000 and 22579200 rates can
> > be set exactly.> 
> >          */
> >         
> >         val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
> >         val &= ~(GENMASK(21, 16) | BIT(0));
> > 
> > -       writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
> > +       writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
> > 
> >         /*
> >         
> >          * First clock parent (osc32K) is unusable for CEC. But since
> >          there
> > 
> > --
> > 2.23.0
> > 
> > --
> > You received this message because you are subscribed to the Google Groups
> > "linux-sunxi" group. To unsubscribe from this group and stop receiving
> > emails from it, send an email to
> > linux-sunxi+unsubscribe@googlegroups.com. To view this discussion on the
> > web, visit
> > https://groups.google.com/d/msgid/linux-sunxi/20190914135100.327412-1-jer
> > nej.skrabec%40siol.net.
Chen-Yu Tsai Sept. 18, 2019, 5:46 a.m. UTC | #3
On Wed, Sep 18, 2019 at 1:21 PM Jernej Škrabec <jernej.skrabec@siol.net> wrote:
>
> Dne torek, 17. september 2019 ob 08:54:08 CEST je Chen-Yu Tsai napisal(a):
> > On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec <jernej.skrabec@siol.net>
> wrote:
> > > Audio devices needs exact clock rates in order to correctly reproduce
> > > the sound. Until now, only integer factors were used to configure H6
> > > audio PLL which resulted in inexact rates. Fix that by adding support
> > > for fractional factors using sigma-delta modulation look-up table. It
> > > contains values for two most commonly used audio base frequencies.
> > >
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > ---
> > >
> > >  drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
> > >  1 file changed, 15 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > > b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index d89353a3cdec..ed6338d74474
> > > 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > > @@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
> > >
> > >   * hardcode it to match with the clock names.
> > >   */
> > >
> > >  #define SUN50I_H6_PLL_AUDIO_REG                0x078
> > >
> > > +
> > > +static struct ccu_sdm_setting pll_audio_sdm_table[] = {
> > > +       { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
> > > +       { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
> > > +};
> > > +
> > >
> > >  static struct ccu_nm pll_audio_base_clk = {
> > >
> > >         .enable         = BIT(31),
> > >         .lock           = BIT(28),
> > >         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> > >         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
> > >
> > > +       .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table,
> > > +                                        BIT(24), 0x178, BIT(31)),
> > >
> > >         .common         = {
> > >
> > > +               .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
> > >
> > >                 .reg            = 0x078,
> > >                 .hw.init        = CLK_HW_INIT("pll-audio-base", "osc24M",
> > >
> > >                                               &ccu_nm_ops,
> > >
> > > @@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] =
> > > {>
> > >  };
> > >
> > >  /*
> > >
> > > - * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
> > > - * fixed post-divider 2.
> > > + * The divider of pll-audio is fixed to 24 for now, so 24576000 and
> > > 22579200 + * rates can be set exactly in conjunction with sigma-delta
> > > modulation.>
> > >   */
> > >
> > >  static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
> > >
> > >                             clk_parent_pll_audio,
> > >
> > > -                           8, 1, CLK_SET_RATE_PARENT);
> > > +                           24, 1, CLK_SET_RATE_PARENT);
> > >
> > >  static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
> > >
> > >                             clk_parent_pll_audio,
> > >                             4, 1, CLK_SET_RATE_PARENT);
> >
> > You need to fix the factors for the other two outputs as well, since all
> > three are derived from pll-audio-base.
>
> Fix how? pll-audio-2x and pll-audio-4x clocks have fixed divider in regards to
> pll-audio-base, while pll-audio has not. Unless you mean changing their name?

Argh... I got it wrong. It looks good actually.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard Sept. 19, 2019, 6:18 p.m. UTC | #4
On Wed, Sep 18, 2019 at 01:46:34PM +0800, Chen-Yu Tsai wrote:
> On Wed, Sep 18, 2019 at 1:21 PM Jernej Škrabec <jernej.skrabec@siol.net> wrote:
> >
> > Dne torek, 17. september 2019 ob 08:54:08 CEST je Chen-Yu Tsai napisal(a):
> > > On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec <jernej.skrabec@siol.net>
> > wrote:
> > > > Audio devices needs exact clock rates in order to correctly reproduce
> > > > the sound. Until now, only integer factors were used to configure H6
> > > > audio PLL which resulted in inexact rates. Fix that by adding support
> > > > for fractional factors using sigma-delta modulation look-up table. It
> > > > contains values for two most commonly used audio base frequencies.
> > > >
> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > > ---
> > > >
> > > >  drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
> > > >  1 file changed, 15 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > > > b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index d89353a3cdec..ed6338d74474
> > > > 100644
> > > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> > > > @@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
> > > >
> > > >   * hardcode it to match with the clock names.
> > > >   */
> > > >
> > > >  #define SUN50I_H6_PLL_AUDIO_REG                0x078
> > > >
> > > > +
> > > > +static struct ccu_sdm_setting pll_audio_sdm_table[] = {
> > > > +       { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
> > > > +       { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
> > > > +};
> > > > +
> > > >
> > > >  static struct ccu_nm pll_audio_base_clk = {
> > > >
> > > >         .enable         = BIT(31),
> > > >         .lock           = BIT(28),
> > > >         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> > > >         .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
> > > >
> > > > +       .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table,
> > > > +                                        BIT(24), 0x178, BIT(31)),
> > > >
> > > >         .common         = {
> > > >
> > > > +               .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
> > > >
> > > >                 .reg            = 0x078,
> > > >                 .hw.init        = CLK_HW_INIT("pll-audio-base", "osc24M",
> > > >
> > > >                                               &ccu_nm_ops,
> > > >
> > > > @@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] =
> > > > {>
> > > >  };
> > > >
> > > >  /*
> > > >
> > > > - * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
> > > > - * fixed post-divider 2.
> > > > + * The divider of pll-audio is fixed to 24 for now, so 24576000 and
> > > > 22579200 + * rates can be set exactly in conjunction with sigma-delta
> > > > modulation.>
> > > >   */
> > > >
> > > >  static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
> > > >
> > > >                             clk_parent_pll_audio,
> > > >
> > > > -                           8, 1, CLK_SET_RATE_PARENT);
> > > > +                           24, 1, CLK_SET_RATE_PARENT);
> > > >
> > > >  static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
> > > >
> > > >                             clk_parent_pll_audio,
> > > >                             4, 1, CLK_SET_RATE_PARENT);
> > >
> > > You need to fix the factors for the other two outputs as well, since all
> > > three are derived from pll-audio-base.
> >
> > Fix how? pll-audio-2x and pll-audio-4x clocks have fixed divider in regards to
> > pll-audio-base, while pll-audio has not. Unless you mean changing their name?
>
> Argh... I got it wrong. It looks good actually.
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Queued for 5.5, thanks

Maxime

Patch
diff mbox series

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index d89353a3cdec..ed6338d74474 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -203,12 +203,21 @@  static struct ccu_nkmp pll_hsic_clk = {
  * hardcode it to match with the clock names.
  */
 #define SUN50I_H6_PLL_AUDIO_REG		0x078
+
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+	{ .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
+	{ .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
+};
+
 static struct ccu_nm pll_audio_base_clk = {
 	.enable		= BIT(31),
 	.lock		= BIT(28),
 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
+	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table,
+					 BIT(24), 0x178, BIT(31)),
 	.common		= {
+		.features	= CCU_FEATURE_SIGMA_DELTA_MOD,
 		.reg		= 0x078,
 		.hw.init	= CLK_HW_INIT("pll-audio-base", "osc24M",
 					      &ccu_nm_ops,
@@ -753,12 +762,12 @@  static const struct clk_hw *clk_parent_pll_audio[] = {
 };
 
 /*
- * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
- * fixed post-divider 2.
+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
+ * rates can be set exactly in conjunction with sigma-delta modulation.
  */
 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
 			    clk_parent_pll_audio,
-			    8, 1, CLK_SET_RATE_PARENT);
+			    24, 1, CLK_SET_RATE_PARENT);
 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
 			    clk_parent_pll_audio,
 			    4, 1, CLK_SET_RATE_PARENT);
@@ -1215,12 +1224,12 @@  static int sun50i_h6_ccu_probe(struct platform_device *pdev)
 	}
 
 	/*
-	 * Force the post-divider of pll-audio to 8 and the output divider
-	 * of it to 1, to make the clock name represents the real frequency.
+	 * Force the post-divider of pll-audio to 12 and the output divider
+	 * of it to 2, so 24576000 and 22579200 rates can be set exactly.
 	 */
 	val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
 	val &= ~(GENMASK(21, 16) | BIT(0));
-	writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
+	writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
 
 	/*
 	 * First clock parent (osc32K) is unusable for CEC. But since there