@@ -13,8 +13,15 @@
*/
#include "qemu/osdep.h"
+#include "sysemu/numa.h"
+#include "hw/acpi/acpi.h"
+#include "hw/firmware/smbios.h"
+#include "hw/i386/pc.h"
#include "hw/i386/fw_cfg.h"
+#include "hw/timer/hpet.h"
#include "hw/nvram/fw_cfg.h"
+#include "e820_memory_layout.h"
+#include "kvm_i386.h"
const char *fw_cfg_arch_key_name(uint16_t key)
{
@@ -36,3 +43,133 @@ const char *fw_cfg_arch_key_name(uint16_t key)
}
return NULL;
}
+
+void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
+{
+ uint8_t *smbios_tables, *smbios_anchor;
+ size_t smbios_tables_len, smbios_anchor_len;
+ struct smbios_phys_mem_area *mem_array;
+ unsigned i, array_count;
+ X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
+
+ /* tell smbios about cpuid version and features */
+ smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
+
+ smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
+ if (smbios_tables) {
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
+ smbios_tables, smbios_tables_len);
+ }
+
+ /* build the array of physical mem area from e820 table */
+ mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
+ for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
+ uint64_t addr, len;
+
+ if (e820_get_entry(i, E820_RAM, &addr, &len)) {
+ mem_array[array_count].address = addr;
+ mem_array[array_count].length = len;
+ array_count++;
+ }
+ }
+ smbios_get_tables(ms, mem_array, array_count,
+ &smbios_tables, &smbios_tables_len,
+ &smbios_anchor, &smbios_anchor_len);
+ g_free(mem_array);
+
+ if (smbios_anchor) {
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
+ smbios_tables, smbios_tables_len);
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
+ smbios_anchor, smbios_anchor_len);
+ }
+}
+
+FWCfgState *fw_cfg_arch_create(MachineState *ms,
+ uint16_t boot_cpus,
+ uint16_t apic_id_limit)
+{
+ FWCfgState *fw_cfg;
+ uint64_t *numa_fw_cfg;
+ int i;
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+ const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
+ int nb_numa_nodes = ms->numa_state->num_nodes;
+
+ fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
+ &address_space_memory);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
+
+ /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
+ *
+ * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
+ * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
+ * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
+ * for CPU hotplug also uses APIC ID and not "CPU index".
+ * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
+ * but the "limit to the APIC ID values SeaBIOS may see".
+ *
+ * So for compatibility reasons with old BIOSes we are stuck with
+ * "etc/max-cpus" actually being apic_id_limit
+ */
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
+ acpi_tables, acpi_tables_len);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
+
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
+ &e820_reserve, sizeof(e820_reserve));
+ fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
+ sizeof(struct e820_entry) * e820_get_num_entries());
+
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
+ /* allocate memory for the NUMA channel: one (64bit) word for the number
+ * of nodes, one word for each VCPU->node and one word for each node to
+ * hold the amount of memory.
+ */
+ numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
+ numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
+ for (i = 0; i < cpus->len; i++) {
+ unsigned int apic_id = cpus->cpus[i].arch_id;
+ assert(apic_id < apic_id_limit);
+ numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
+ }
+ for (i = 0; i < nb_numa_nodes; i++) {
+ numa_fw_cfg[apic_id_limit + 1 + i] =
+ cpu_to_le64(ms->numa_state->nodes[i].node_mem);
+ }
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
+ (1 + apic_id_limit + nb_numa_nodes) *
+ sizeof(*numa_fw_cfg));
+
+ return fw_cfg;
+}
+
+void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
+{
+ X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
+ CPUX86State *env = &cpu->env;
+ uint32_t unused, ecx, edx;
+ uint64_t feature_control_bits = 0;
+ uint64_t *val;
+
+ cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
+ if (ecx & CPUID_EXT_VMX) {
+ feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
+ }
+
+ if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
+ (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
+ (env->mcg_cap & MCG_LMCE_P)) {
+ feature_control_bits |= FEATURE_CONTROL_LMCE;
+ }
+
+ if (!feature_control_bits) {
+ return;
+ }
+
+ val = g_malloc(sizeof(*val));
+ *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
+ fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
+}
@@ -9,6 +9,7 @@
#ifndef HW_I386_FW_CFG_H
#define HW_I386_FW_CFG_H
+#include "hw/boards.h"
#include "hw/nvram/fw_cfg.h"
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
@@ -17,4 +18,10 @@
#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
+FWCfgState *fw_cfg_arch_create(MachineState *ms,
+ uint16_t boot_cpus,
+ uint16_t apic_id_limit);
+void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg);
+void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg);
+
#endif
@@ -88,6 +88,7 @@
#include "qapi/qmp/qerror.h"
#include "config-devices.h"
#include "e820_memory_layout.h"
+#include "fw_cfg.h"
/* debug PC/ISA interrupts */
//#define DEBUG_IRQ
@@ -894,108 +895,6 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
}
}
-static void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
-{
- uint8_t *smbios_tables, *smbios_anchor;
- size_t smbios_tables_len, smbios_anchor_len;
- struct smbios_phys_mem_area *mem_array;
- unsigned i, array_count;
- X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
-
- /* tell smbios about cpuid version and features */
- smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
-
- smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
- if (smbios_tables) {
- fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
- smbios_tables, smbios_tables_len);
- }
-
- /* build the array of physical mem area from e820 table */
- mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
- for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
- uint64_t addr, len;
-
- if (e820_get_entry(i, E820_RAM, &addr, &len)) {
- mem_array[array_count].address = addr;
- mem_array[array_count].length = len;
- array_count++;
- }
- }
- smbios_get_tables(ms, mem_array, array_count,
- &smbios_tables, &smbios_tables_len,
- &smbios_anchor, &smbios_anchor_len);
- g_free(mem_array);
-
- if (smbios_anchor) {
- fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
- smbios_tables, smbios_tables_len);
- fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
- smbios_anchor, smbios_anchor_len);
- }
-}
-
-static FWCfgState *fw_cfg_arch_create(MachineState *ms,
- uint16_t boot_cpus,
- uint16_t apic_id_limit)
-{
- FWCfgState *fw_cfg;
- uint64_t *numa_fw_cfg;
- int i;
- MachineClass *mc = MACHINE_GET_CLASS(ms);
- const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
- int nb_numa_nodes = ms->numa_state->num_nodes;
-
- fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
- &address_space_memory);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
-
- /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
- *
- * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
- * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
- * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
- * for CPU hotplug also uses APIC ID and not "CPU index".
- * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
- * but the "limit to the APIC ID values SeaBIOS may see".
- *
- * So for compatibility reasons with old BIOSes we are stuck with
- * "etc/max-cpus" actually being apic_id_limit
- */
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
- fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
- acpi_tables, acpi_tables_len);
- fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
-
- fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
- &e820_reserve, sizeof(e820_reserve));
- fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
- sizeof(struct e820_entry) * e820_get_num_entries());
-
- fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
- /* allocate memory for the NUMA channel: one (64bit) word for the number
- * of nodes, one word for each VCPU->node and one word for each node to
- * hold the amount of memory.
- */
- numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
- numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
- for (i = 0; i < cpus->len; i++) {
- unsigned int apic_id = cpus->cpus[i].arch_id;
- assert(apic_id < apic_id_limit);
- numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
- }
- for (i = 0; i < nb_numa_nodes; i++) {
- numa_fw_cfg[apic_id_limit + 1 + i] =
- cpu_to_le64(ms->numa_state->nodes[i].node_mem);
- }
- fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
- (1 + apic_id_limit + nb_numa_nodes) *
- sizeof(*numa_fw_cfg));
-
- return fw_cfg;
-}
-
static long get_file_size(FILE *f)
{
long where, size;
@@ -1623,35 +1522,6 @@ void pc_cpus_init(PCMachineState *pcms)
}
}
-static void fw_cfg_build_feature_control(MachineState *ms,
- FWCfgState *fw_cfg)
-{
- X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
- CPUX86State *env = &cpu->env;
- uint32_t unused, ecx, edx;
- uint64_t feature_control_bits = 0;
- uint64_t *val;
-
- cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
- if (ecx & CPUID_EXT_VMX) {
- feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
- }
-
- if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
- (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
- (env->mcg_cap & MCG_LMCE_P)) {
- feature_control_bits |= FEATURE_CONTROL_LMCE;
- }
-
- if (!feature_control_bits) {
- return;
- }
-
- val = g_malloc(sizeof(*val));
- *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
- fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
-}
-
static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
{
if (cpus_count > 0xff) {