[5/6] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
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Message ID 20190917121155.13197-6-radhakrishna.sripada@intel.com
State New
Headers show
Series
  • Clear Color Support for TGL Render Decompression
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Commit Message

Sripada, Radhakrishna Sept. 17, 2019, 12:11 p.m. UTC
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.

V2: Description changes as suggested by Rafael.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

Patch
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diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ec8351922265..f2b79cf749a4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -430,6 +430,17 @@  extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
+ * main surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *