[v2,1/3] drm/i915/display: Fix formatting issues
diff mbox series

Message ID 1568724525-19275-2-git-send-email-swati2.sharma@intel.com
State New
Headers show
Series
  • adding gamma state checker for icl+ platforms
Related show

Commit Message

Swati Sharma Sept. 17, 2019, 12:48 p.m. UTC
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

Comments

Jani Nikula Sept. 18, 2019, 8:13 a.m. UTC | #1
Subject prefix "drm/i915/display" is a fairly broad
statement. "drm/i915/color" perhaps.

Please add a commit message. See git log. We don't approve of empty
commit messages.

On Tue, 17 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 318308d..b1f0f7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>  	u32 i;
>  
>  	/*
> -	 * Every entry in the multi-segment LUT is corresponding to a superfine
> -	 * segment step which is 1/(8 * 128 * 256).
> +	 * Program Super Fine segment (let's call it seg1)...
>  	 *
> -	 * Superfine segment has 9 entries, corresponding to values
> -	 * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
> +	 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
> +	 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
> +	 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
>  	 */
>  	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
>  
> @@ -837,10 +837,9 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>  	u32 i;
>  
>  	/*
> -	 *
>  	 * Program Fine segment (let's call it seg2)...
>  	 *
> -	 * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256),  2/(128*256)
> +	 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256),  2/(128*256)
	                                                            ^
Since you're cleaning this up... extra space there. And some of the
items have (128 * 256) and others (128*256).

I wouldn't care otherwise, but why fix some punctuation and leave this
behind.

>  	 * ... 256/(128*256). So in order to program fine segment of LUT we
>  	 * need to pick every 8'th entry in LUT, and program 256 indexes.
>  	 *
> @@ -858,7 +857,7 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>  	 * Program Coarse segment (let's call it seg3)...
>  	 *
>  	 * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
> -	 * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
> +	 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
>  	 * above, we need to pick every (8 * 128)th entry in LUT, and
>  	 * program 256 of those.
>  	 *
> @@ -890,12 +889,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>  	case GAMMA_MODE_MODE_8BIT:
>  		i9xx_load_luts(crtc_state);
>  		break;
> -
>  	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
>  		icl_program_gamma_superfine_segment(crtc_state);
>  		icl_program_gamma_multi_segment(crtc_state);
>  		break;
> -
>  	default:
>  		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
>  		ivb_load_lut_ext_max(crtc);

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 318308d..b1f0f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -807,11 +807,11 @@  static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 	u32 i;
 
 	/*
-	 * Every entry in the multi-segment LUT is corresponding to a superfine
-	 * segment step which is 1/(8 * 128 * 256).
+	 * Program Super Fine segment (let's call it seg1)...
 	 *
-	 * Superfine segment has 9 entries, corresponding to values
-	 * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
+	 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
+	 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
+	 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
 	 */
 	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
 
@@ -837,10 +837,9 @@  static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 	u32 i;
 
 	/*
-	 *
 	 * Program Fine segment (let's call it seg2)...
 	 *
-	 * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256),  2/(128*256)
+	 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256),  2/(128*256)
 	 * ... 256/(128*256). So in order to program fine segment of LUT we
 	 * need to pick every 8'th entry in LUT, and program 256 indexes.
 	 *
@@ -858,7 +857,7 @@  static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 	 * Program Coarse segment (let's call it seg3)...
 	 *
 	 * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
-	 * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
+	 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
 	 * above, we need to pick every (8 * 128)th entry in LUT, and
 	 * program 256 of those.
 	 *
@@ -890,12 +889,10 @@  static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 	case GAMMA_MODE_MODE_8BIT:
 		i9xx_load_luts(crtc_state);
 		break;
-
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
 		icl_program_gamma_multi_segment(crtc_state);
 		break;
-
 	default:
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc);