[v2,2/4] dt-bindings: snps,dw-apb-ssi: Add optional clock domain information
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Message ID 1568793876-9009-3-git-send-email-gareth.williams.jx@renesas.com
State Accepted
Commit 47cf13bc763c891c6192184c5e5aa8c1b331b2ff
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Series
  • spi: dw: Add basic runtime PM support
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Commit Message

Gareth Williams Sept. 18, 2019, 8:04 a.m. UTC
Note in the bindings documentation that pclk should be renamed if a clock
domain is used to enable the optional bus clock.

Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
---
v2: Introduced this patch.
---
 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Rob Herring Oct. 1, 2019, 12:02 p.m. UTC | #1
On Wed, Sep 18, 2019 at 09:04:34AM +0100, Gareth Williams wrote:
> Note in the bindings documentation that pclk should be renamed if a clock
> domain is used to enable the optional bus clock.
> 
> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
> ---
> v2: Introduced this patch.
> ---
>  Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> index f54c8c3..3ed08ee 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> @@ -16,7 +16,8 @@ Required properties:
>  Optional properties:
>  - clock-names : Contains the names of the clocks:
>      "ssi_clk", for the core clock used to generate the external SPI clock.
> -    "pclk", the interface clock, required for register access.
> +    "pclk", the interface clock, required for register access. If a clock domain
> +     used to enable this clock then it should be named "pclk_clkdomain".

What's a clock domain?

Unless this is a h/w difference in the IP block, then this change 
doesn't make sense.

>  - cs-gpios : Specifies the gpio pins to be used for chipselects.
>  - num-cs : The number of chipselects. If omitted, this will default to 4.
>  - reg-io-width : The I/O register width (in bytes) implemented by this
> -- 
> 2.7.4
>
Gareth Williams Oct. 1, 2019, 1:50 p.m. UTC | #2
Hi Rob,

On Tue, Oct 01, 2019 at 13:02:34AM +0100, Rob Herring wrote:
> On Wed, Sep 18, 2019 at 09:04:34AM +0100, Gareth Williams wrote:
> > Note in the bindings documentation that pclk should be renamed if a
> > clock domain is used to enable the optional bus clock.
> >
> > Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
> > ---
> > v2: Introduced this patch.
> > ---
> >  Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > index f54c8c3..3ed08ee 100644
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > @@ -16,7 +16,8 @@ Required properties:
> >  Optional properties:
> >  - clock-names : Contains the names of the clocks:
> >      "ssi_clk", for the core clock used to generate the external SPI clock.
> > -    "pclk", the interface clock, required for register access.
> > +    "pclk", the interface clock, required for register access. If a clock domain
> > +     used to enable this clock then it should be named "pclk_clkdomain".
> 
> What's a clock domain?
> 
> Unless this is a h/w difference in the IP block, then this change doesn't make
> sense.
This is a reference to the use of clock domains that are implemented through
generic power domains. The domain is implemented in 
drivers/clk/renesas/r9a06g032-clocks.c and general details of clock domains
can be found at 
https://elinux.org/images/1/14/Last_One_Out%2C_Turn_Off_The_Lights.pdf

> 
> >  - cs-gpios : Specifies the gpio pins to be used for chipselects.
> >  - num-cs : The number of chipselects. If omitted, this will default to 4.
> >  - reg-io-width : The I/O register width (in bytes) implemented by
> > this
> > --
> > 2.7.4
> >
Geert Uytterhoeven Oct. 1, 2019, 2:51 p.m. UTC | #3
Hi Gareth,

On Tue, Oct 1, 2019 at 3:50 PM Gareth Williams
<gareth.williams.jx@renesas.com> wrote:
> On Tue, Oct 01, 2019 at 13:02:34AM +0100, Rob Herring wrote:
> > On Wed, Sep 18, 2019 at 09:04:34AM +0100, Gareth Williams wrote:
> > > Note in the bindings documentation that pclk should be renamed if a
> > > clock domain is used to enable the optional bus clock.
> > >
> > > Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
> > > ---
> > > v2: Introduced this patch.
> > > ---
> > >  Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > > b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > > index f54c8c3..3ed08ee 100644
> > > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > > @@ -16,7 +16,8 @@ Required properties:
> > >  Optional properties:
> > >  - clock-names : Contains the names of the clocks:
> > >      "ssi_clk", for the core clock used to generate the external SPI clock.
> > > -    "pclk", the interface clock, required for register access.
> > > +    "pclk", the interface clock, required for register access. If a clock domain
> > > +     used to enable this clock then it should be named "pclk_clkdomain".
> >
> > What's a clock domain?
> >
> > Unless this is a h/w difference in the IP block, then this change doesn't make
> > sense.
> This is a reference to the use of clock domains that are implemented through
> generic power domains. The domain is implemented in
> drivers/clk/renesas/r9a06g032-clocks.c and general details of clock domains
> can be found at
> https://elinux.org/images/1/14/Last_One_Out%2C_Turn_Off_The_Lights.pdf

Rob is right: the clock domain is an SoC integration detail, not specific to
the snps,dw-apb-ssi block.
Remember, DT describes hardware, not implementation details.

So the Linux snps,dw-apb-ssi driver should take care of it.

Which brings us back to an old discussion topic: power-domains properties
describe integration, and thus should be documented at a higher level than
in individual binding documents, just like e.g. interrupt-parent.

Gr{oetje,eeting}s,

                        Geert

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index f54c8c3..3ed08ee 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -16,7 +16,8 @@  Required properties:
 Optional properties:
 - clock-names : Contains the names of the clocks:
     "ssi_clk", for the core clock used to generate the external SPI clock.
-    "pclk", the interface clock, required for register access.
+    "pclk", the interface clock, required for register access. If a clock domain
+     used to enable this clock then it should be named "pclk_clkdomain".
 - cs-gpios : Specifies the gpio pins to be used for chipselects.
 - num-cs : The number of chipselects. If omitted, this will default to 4.
 - reg-io-width : The I/O register width (in bytes) implemented by this