| Message ID | 20190919000726.267988-13-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | TGL TC enabling v2 | expand |
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e6a7280da408..2379290ee6f2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2630,7 +2630,12 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, continue; if (div2 >= 2) { if (is_dkl) { - a_divratio = 5; + /* + * Note: a_divratio not matching TGL + * BSpec algorithm but matching + * hardcoded values and working on HW + */ + a_divratio = 10; tlinedrv = 1; } else { a_divratio = is_dp ? 10 : 5;
Link training is failling when running link at 2.7GHz and 1.62GHz and following BSpec pll algorithm. Comparing the values calculated and the ones from the reference table it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on div2 value, that matches with dkl hardcoded table. So implementing this way as it proved to work in HW and leaving a comment so we know why it do not match BSpec. Issue reported on BSpec 49204. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)