dt-bindings: irqchip: renesas: intc-irqpin: convert bindings to json-schema
diff mbox series

Message ID 1569008061-10459-1-git-send-email-ykaneko0929@gmail.com
State Superseded
Delegated to: Geert Uytterhoeven
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Series
  • dt-bindings: irqchip: renesas: intc-irqpin: convert bindings to json-schema
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Commit Message

Yoshihiro Kaneko Sept. 20, 2019, 7:34 p.m. UTC
Convert R-/SH-Mobile IRQPin Controller bindings documentation to json-schema.

Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
 .../interrupt-controller/renesas,intc-irqpin.txt   |  62 -------------
 .../interrupt-controller/renesas,intc-irqpin.yaml  | 102 +++++++++++++++++++++
 2 files changed, 102 insertions(+), 62 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml

Comments

Simon Horman Sept. 23, 2019, 11:30 a.m. UTC | #1
On Sat, Sep 21, 2019 at 04:34:21AM +0900, Yoshihiro Kaneko wrote:
> Convert R-/SH-Mobile IRQPin Controller bindings documentation to json-schema.
> 
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> ---
>  .../interrupt-controller/renesas,intc-irqpin.txt   |  62 -------------
>  .../interrupt-controller/renesas,intc-irqpin.yaml  | 102 +++++++++++++++++++++
>  2 files changed, 102 insertions(+), 62 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> deleted file mode 100644
> index 772c550..0000000
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -DT bindings for the R-/SH-Mobile irqpin controller
> -
> -Required properties:
> -
> -- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
> -  as fallback.
> -  Examples with soctypes are:
> -    - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
> -    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
> -    - "renesas,intc-irqpin-r8a7779" (R-Car H1)
> -    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
> -
> -- reg: Base address and length of each register bank used by the external
> -  IRQ pins driven by the interrupt controller hardware module. The base
> -  addresses, length and number of required register banks varies with soctype.
> -- interrupt-controller: Identifies the node as an interrupt controller.
> -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
> -  interrupts.txt in this directory.
> -- interrupts: Must contain a list of interrupt specifiers. For each interrupt
> -  provided by this irqpin controller instance, there must be one entry,
> -  referring to the corresponding parent interrupt.
> -
> -Optional properties:
> -
> -- any properties, listed in interrupts.txt, and any standard resource allocation
> -  properties
> -- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
> -  if different from the default 4 bits
> -- control-parent: disable and enable interrupts on the parent interrupt
> -  controller, needed for some broken implementations
> -- clocks: Must contain a reference to the functional clock.  This property is
> -  mandatory if the hardware implements a controllable functional clock for
> -  the irqpin controller instance.
> -- power-domains: Must contain a reference to the power domain. This property is
> -  mandatory if the irqpin controller instance is part of a controllable power
> -  domain.
> -
> -
> -Example
> --------
> -
> -	irqpin1: interrupt-controller@e6900004 {
> -		compatible = "renesas,intc-irqpin-r8a7740",
> -			     "renesas,intc-irqpin";
> -		#interrupt-cells = <2>;
> -		interrupt-controller;
> -		reg = <0xe6900004 4>,
> -			<0xe6900014 4>,
> -			<0xe6900024 1>,
> -			<0xe6900044 1>,
> -			<0xe6900064 1>;
> -		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH
> -			      0 149 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
> -		power-domains = <&pd_a4s>;
> -	};
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> new file mode 100644
> index 0000000..d4d3cf8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DT bindings for the R-/SH-Mobile irqpin controller
> +
> +maintainers:
> +  - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

I guess Geert's email address got fuzzed somehow.

> +  - Guennadi Liakhovetski <g.liakhovetski@gmx.de>

I believe that its been a while since Guennadi worked in this area.
I'd suggest not including him as a maintainer of this binding.

> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,intc-irqpin-r8a7740  # R-Mobile A1
> +          - renesas,intc-irqpin-r8a7778  # R-Car M1A
> +          - renesas,intc-irqpin-r8a7779  # R-Car H1
> +          - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
> +      - const: renesas,intc-irqpin
> +
> +  reg:
> +    # Base address and length of each register bank used by the external
> +    # IRQ pins driven by the interrupt controller hardware module. The base
> +    # addresses, length and number of required register banks varies with
> +    # soctype.
> +    minItems: 1
> +    maxItems: 6
> +
> +  interrupt-controller: true
> +    # Identifies the node as an interrupt controller.
> +
> +  '#interrupt-cells':
> +    # an interrupt index and flags, as defined in interrupts.txt in this
> +    # directory.
> +    const: 2
> +
> +  interrupts:
> +    # Must contain a list of interrupt specifiers. For each interrupt
> +    # provided by this irqpin controller instance, there must be one entry,
> +    # referring to the corresponding parent interrupt.
> +    maxItems: 1
> +
> +  sense-bitfield-width:
> +    # width of a single sense bitfield in the SENSE register, if different
> +    # from the default 4 bits
> +    maxItems: 1

I wonder if we need to give this field a type, something like this?

  sense-bitfield-width:
    # Comment
    $ref: /schemas/types.yaml#/definitions/uint32
    maxItems: 1

    Also, I wonder if there should be some constraints on the values.
    (I don't know if these constraints are correct)

    minimum: 1
    maximum: 64
    default: 4

> +
> +  control-parent:
> +    # disable and enable interrupts on the parent interrupt controller,
> +    # needed for some broken implementations
> +    maxItems: 1

I think we can describe this as a boolean.

  control-parent:
     # Comment
     type: boolean


> +
> +  clocks:
> +    # Must contain a reference to the functional clock.  This property is
> +    # mandatory if the hardware implements a controllable functional clock for
> +    # the irqpin controller instance.
> +    maxItems: 1
> +
> +  power-domains:
> +    # Must contain a reference to the power domain. This property is
> +    # mandatory if the irqpin controller instance is part of a controllable
> +    # power domain.
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +  - interrupts

Is 'clocks' also required?

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r8a7740-clock.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    irqpin1: interrupt-controller@e6900004 {
> +        compatible = "renesas,intc-irqpin-r8a7740",
> +                     "renesas,intc-irqpin";
> +        #interrupt-cells = <2>;
> +        interrupt-controller;
> +        reg = <0xe6900004 4>,
> +              <0xe6900014 4>,
> +              <0xe6900024 1>,
> +              <0xe6900044 1>,
> +              <0xe6900064 1>;
> +        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
> +        power-domains = <&pd_a4s>;
> +    };
> -- 
> 1.9.1
>
Yoshihiro Kaneko Sept. 26, 2019, 7:11 p.m. UTC | #2
Hi Simon-san,

Thank you for your review.

2019年9月23日(月) 20:30 Simon Horman <horms@verge.net.au>:
>
> On Sat, Sep 21, 2019 at 04:34:21AM +0900, Yoshihiro Kaneko wrote:
> > Convert R-/SH-Mobile IRQPin Controller bindings documentation to json-schema.
> >
> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > ---
> >  .../interrupt-controller/renesas,intc-irqpin.txt   |  62 -------------
> >  .../interrupt-controller/renesas,intc-irqpin.yaml  | 102 +++++++++++++++++++++
> >  2 files changed, 102 insertions(+), 62 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> > deleted file mode 100644
> > index 772c550..0000000
> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> > +++ /dev/null
> > @@ -1,62 +0,0 @@
> > -DT bindings for the R-/SH-Mobile irqpin controller
> > -
> > -Required properties:
> > -
> > -- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
> > -  as fallback.
> > -  Examples with soctypes are:
> > -    - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
> > -    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
> > -    - "renesas,intc-irqpin-r8a7779" (R-Car H1)
> > -    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
> > -
> > -- reg: Base address and length of each register bank used by the external
> > -  IRQ pins driven by the interrupt controller hardware module. The base
> > -  addresses, length and number of required register banks varies with soctype.
> > -- interrupt-controller: Identifies the node as an interrupt controller.
> > -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
> > -  interrupts.txt in this directory.
> > -- interrupts: Must contain a list of interrupt specifiers. For each interrupt
> > -  provided by this irqpin controller instance, there must be one entry,
> > -  referring to the corresponding parent interrupt.
> > -
> > -Optional properties:
> > -
> > -- any properties, listed in interrupts.txt, and any standard resource allocation
> > -  properties
> > -- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
> > -  if different from the default 4 bits
> > -- control-parent: disable and enable interrupts on the parent interrupt
> > -  controller, needed for some broken implementations
> > -- clocks: Must contain a reference to the functional clock.  This property is
> > -  mandatory if the hardware implements a controllable functional clock for
> > -  the irqpin controller instance.
> > -- power-domains: Must contain a reference to the power domain. This property is
> > -  mandatory if the irqpin controller instance is part of a controllable power
> > -  domain.
> > -
> > -
> > -Example
> > --------
> > -
> > -     irqpin1: interrupt-controller@e6900004 {
> > -             compatible = "renesas,intc-irqpin-r8a7740",
> > -                          "renesas,intc-irqpin";
> > -             #interrupt-cells = <2>;
> > -             interrupt-controller;
> > -             reg = <0xe6900004 4>,
> > -                     <0xe6900014 4>,
> > -                     <0xe6900024 1>,
> > -                     <0xe6900044 1>,
> > -                     <0xe6900064 1>;
> > -             interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH
> > -                           0 149 IRQ_TYPE_LEVEL_HIGH>;
> > -             clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
> > -             power-domains = <&pd_a4s>;
> > -     };
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> > new file mode 100644
> > index 0000000..d4d3cf8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: DT bindings for the R-/SH-Mobile irqpin controller
> > +
> > +maintainers:
> > +  - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> I guess Geert's email address got fuzzed somehow.

I will fix it...

>
> > +  - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
>
> I believe that its been a while since Guennadi worked in this area.
> I'd suggest not including him as a maintainer of this binding.

I understood.

>
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,intc-irqpin-r8a7740  # R-Mobile A1
> > +          - renesas,intc-irqpin-r8a7778  # R-Car M1A
> > +          - renesas,intc-irqpin-r8a7779  # R-Car H1
> > +          - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
> > +      - const: renesas,intc-irqpin
> > +
> > +  reg:
> > +    # Base address and length of each register bank used by the external
> > +    # IRQ pins driven by the interrupt controller hardware module. The base
> > +    # addresses, length and number of required register banks varies with
> > +    # soctype.
> > +    minItems: 1
> > +    maxItems: 6
> > +
> > +  interrupt-controller: true
> > +    # Identifies the node as an interrupt controller.
> > +
> > +  '#interrupt-cells':
> > +    # an interrupt index and flags, as defined in interrupts.txt in this
> > +    # directory.
> > +    const: 2
> > +
> > +  interrupts:
> > +    # Must contain a list of interrupt specifiers. For each interrupt
> > +    # provided by this irqpin controller instance, there must be one entry,
> > +    # referring to the corresponding parent interrupt.
> > +    maxItems: 1
> > +
> > +  sense-bitfield-width:
> > +    # width of a single sense bitfield in the SENSE register, if different
> > +    # from the default 4 bits
> > +    maxItems: 1
>
> I wonder if we need to give this field a type, something like this?
>
>   sense-bitfield-width:
>     # Comment
>     $ref: /schemas/types.yaml#/definitions/uint32
>     maxItems: 1

I will do it.

>
>     Also, I wonder if there should be some constraints on the values.
>     (I don't know if these constraints are correct)
>
>     minimum: 1
>     maximum: 64
>     default: 4

I don't know the correct maximum value.

>
> > +
> > +  control-parent:
> > +    # disable and enable interrupts on the parent interrupt controller,
> > +    # needed for some broken implementations
> > +    maxItems: 1
>
> I think we can describe this as a boolean.
>
>   control-parent:
>      # Comment
>      type: boolean

I will do it.

>
>
> > +
> > +  clocks:
> > +    # Must contain a reference to the functional clock.  This property is
> > +    # mandatory if the hardware implements a controllable functional clock for
> > +    # the irqpin controller instance.
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    # Must contain a reference to the power domain. This property is
> > +    # mandatory if the irqpin controller instance is part of a controllable
> > +    # power domain.
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupt-controller
> > +  - '#interrupt-cells'
> > +  - interrupts
>
> Is 'clocks' also required?

It is explained that 'clocks' is optional in renesas,intc-irqpin.txt.
In fact, 'clocks' is not defined in the irqpin node of r8a7778.dtsi
and r8a7779.dtsi.


Regards,
Kaneko

>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/r8a7740-clock.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +    irqpin1: interrupt-controller@e6900004 {
> > +        compatible = "renesas,intc-irqpin-r8a7740",
> > +                     "renesas,intc-irqpin";
> > +        #interrupt-cells = <2>;
> > +        interrupt-controller;
> > +        reg = <0xe6900004 4>,
> > +              <0xe6900014 4>,
> > +              <0xe6900024 1>,
> > +              <0xe6900044 1>,
> > +              <0xe6900064 1>;
> > +        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > +                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
> > +        power-domains = <&pd_a4s>;
> > +    };
> > --
> > 1.9.1
> >

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
deleted file mode 100644
index 772c550..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
+++ /dev/null
@@ -1,62 +0,0 @@ 
-DT bindings for the R-/SH-Mobile irqpin controller
-
-Required properties:
-
-- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
-  as fallback.
-  Examples with soctypes are:
-    - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
-    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
-    - "renesas,intc-irqpin-r8a7779" (R-Car H1)
-    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
-
-- reg: Base address and length of each register bank used by the external
-  IRQ pins driven by the interrupt controller hardware module. The base
-  addresses, length and number of required register banks varies with soctype.
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
-  interrupts.txt in this directory.
-- interrupts: Must contain a list of interrupt specifiers. For each interrupt
-  provided by this irqpin controller instance, there must be one entry,
-  referring to the corresponding parent interrupt.
-
-Optional properties:
-
-- any properties, listed in interrupts.txt, and any standard resource allocation
-  properties
-- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
-  if different from the default 4 bits
-- control-parent: disable and enable interrupts on the parent interrupt
-  controller, needed for some broken implementations
-- clocks: Must contain a reference to the functional clock.  This property is
-  mandatory if the hardware implements a controllable functional clock for
-  the irqpin controller instance.
-- power-domains: Must contain a reference to the power domain. This property is
-  mandatory if the irqpin controller instance is part of a controllable power
-  domain.
-
-
-Example
--------
-
-	irqpin1: interrupt-controller@e6900004 {
-		compatible = "renesas,intc-irqpin-r8a7740",
-			     "renesas,intc-irqpin";
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		reg = <0xe6900004 4>,
-			<0xe6900014 4>,
-			<0xe6900024 1>,
-			<0xe6900044 1>,
-			<0xe6900064 1>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
-		power-domains = <&pd_a4s>;
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
new file mode 100644
index 0000000..d4d3cf8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
@@ -0,0 +1,102 @@ 
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DT bindings for the R-/SH-Mobile irqpin controller
+
+maintainers:
+  - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
+  - Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,intc-irqpin-r8a7740  # R-Mobile A1
+          - renesas,intc-irqpin-r8a7778  # R-Car M1A
+          - renesas,intc-irqpin-r8a7779  # R-Car H1
+          - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
+      - const: renesas,intc-irqpin
+
+  reg:
+    # Base address and length of each register bank used by the external
+    # IRQ pins driven by the interrupt controller hardware module. The base
+    # addresses, length and number of required register banks varies with
+    # soctype.
+    minItems: 1
+    maxItems: 6
+
+  interrupt-controller: true
+    # Identifies the node as an interrupt controller.
+
+  '#interrupt-cells':
+    # an interrupt index and flags, as defined in interrupts.txt in this
+    # directory.
+    const: 2
+
+  interrupts:
+    # Must contain a list of interrupt specifiers. For each interrupt
+    # provided by this irqpin controller instance, there must be one entry,
+    # referring to the corresponding parent interrupt.
+    maxItems: 1
+
+  sense-bitfield-width:
+    # width of a single sense bitfield in the SENSE register, if different
+    # from the default 4 bits
+    maxItems: 1
+
+  control-parent:
+    # disable and enable interrupts on the parent interrupt controller,
+    # needed for some broken implementations
+    maxItems: 1
+
+  clocks:
+    # Must contain a reference to the functional clock.  This property is
+    # mandatory if the hardware implements a controllable functional clock for
+    # the irqpin controller instance.
+    maxItems: 1
+
+  power-domains:
+    # Must contain a reference to the power domain. This property is
+    # mandatory if the irqpin controller instance is part of a controllable
+    # power domain.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a7740-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    irqpin1: interrupt-controller@e6900004 {
+        compatible = "renesas,intc-irqpin-r8a7740",
+                     "renesas,intc-irqpin";
+        #interrupt-cells = <2>;
+        interrupt-controller;
+        reg = <0xe6900004 4>,
+              <0xe6900014 4>,
+              <0xe6900024 1>,
+              <0xe6900044 1>,
+              <0xe6900064 1>;
+        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+                      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
+        power-domains = <&pd_a4s>;
+    };