clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
diff mbox series

Message ID be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com
State Under Review
Delegated to: Geert Uytterhoeven
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  • clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
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Commit Message

Sergei Shtylyov Sept. 27, 2019, 6:09 p.m. UTC
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...

Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.

 drivers/clk/renesas/rcar-gen3-cpg.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Geert Uytterhoeven Oct. 7, 2019, 11:45 a.m. UTC | #1
Hi Sergei,

On Fri, Sep 27, 2019 at 8:09 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
> clk_register_composite() when registering the RPC[D2] clocks...
>
> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks for your patch!

LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Now, before I apply this: does this make RPC-IF work?

> --- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_r
>
>         clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
>                                      &rpc->div.hw,  &clk_divider_ops,
> -                                    &rpc->gate.hw, &clk_gate_ops, 0);
> +                                    &rpc->gate.hw, &clk_gate_ops,
> +                                    CLK_SET_RATE_PARENT);
>         if (IS_ERR(clk)) {
>                 kfree(rpc);
>                 return clk;
> @@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk
>
>         clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
>                                      &rpcd2->fixed.hw, &clk_fixed_factor_ops,
> -                                    &rpcd2->gate.hw, &clk_gate_ops, 0);
> +                                    &rpcd2->gate.hw, &clk_gate_ops,
> +                                    CLK_SET_RATE_PARENT);
>         if (IS_ERR(clk))
>                 kfree(rpcd2);

Gr{oetje,eeting}s,

                        Geert
Sergei Shtylyov Oct. 7, 2019, 11:49 a.m. UTC | #2
On 10/07/2019 02:45 PM, Geert Uytterhoeven wrote:

>> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
>> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
>> clk_register_composite() when registering the RPC[D2] clocks...
>>
>> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> Thanks for your patch!
> 
> LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

   Thanks. :-)

> Now, before I apply this: does this make RPC-IF work?

   Unfortunately, no. :-/

MBR, Sergei

Patch
diff mbox series

Index: renesas/drivers/clk/renesas/rcar-gen3-cpg.c
===================================================================
--- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c
+++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -464,7 +464,8 @@  static struct clk * __init cpg_rpc_clk_r
 
 	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
 				     &rpc->div.hw,  &clk_divider_ops,
-				     &rpc->gate.hw, &clk_gate_ops, 0);
+				     &rpc->gate.hw, &clk_gate_ops,
+				     CLK_SET_RATE_PARENT);
 	if (IS_ERR(clk)) {
 		kfree(rpc);
 		return clk;
@@ -500,7 +501,8 @@  static struct clk * __init cpg_rpcd2_clk
 
 	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
 				     &rpcd2->fixed.hw, &clk_fixed_factor_ops,
-				     &rpcd2->gate.hw, &clk_gate_ops, 0);
+				     &rpcd2->gate.hw, &clk_gate_ops,
+				     CLK_SET_RATE_PARENT);
 	if (IS_ERR(clk))
 		kfree(rpcd2);