ALSA: hdac: clear link output stream mapping
diff mbox series

Message ID 20190930142945.7805-1-pierre-louis.bossart@linux.intel.com
State New
Headers show
Series
  • ALSA: hdac: clear link output stream mapping
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Commit Message

Pierre-Louis Bossart Sept. 30, 2019, 2:29 p.m. UTC
From: Rander Wang <rander.wang@linux.intel.com>

Fix potential DMA hang upon starting playback on devices in HDA mode
on Intel platforms (Gemini Lake/Whiskey Lake/Comet Lake/Ice Lake). It
doesn't affect platforms before Gemini Lake or any Intel device in
non-HDA mode.

The reset value for the LOSDIV register is all output streams valid.
Clear this register to invalidate non-existent streams when the bus
is powered up.

Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
 include/sound/hda_register.h        | 3 +++
 sound/hda/ext/hdac_ext_controller.c | 5 +++++
 2 files changed, 8 insertions(+)

Comments

Takashi Iwai Oct. 7, 2019, 1:59 a.m. UTC | #1
On Mon, 30 Sep 2019 16:29:45 +0200,
Pierre-Louis Bossart wrote:
> 
> From: Rander Wang <rander.wang@linux.intel.com>
> 
> Fix potential DMA hang upon starting playback on devices in HDA mode
> on Intel platforms (Gemini Lake/Whiskey Lake/Comet Lake/Ice Lake). It
> doesn't affect platforms before Gemini Lake or any Intel device in
> non-HDA mode.
> 
> The reset value for the LOSDIV register is all output streams valid.
> Clear this register to invalidate non-existent streams when the bus
> is powered up.
> 
> Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Applied now.  Thanks.


Takashi

Patch
diff mbox series

diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
index 0fd39295b426..057d2a2d0bd0 100644
--- a/include/sound/hda_register.h
+++ b/include/sound/hda_register.h
@@ -264,6 +264,9 @@  enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define AZX_REG_ML_LOUTPAY		0x20
 #define AZX_REG_ML_LINPAY		0x30
 
+/* bit0 is reserved, with BIT(1) mapping to stream1 */
+#define ML_LOSIDV_STREAM_MASK		0xFFFE
+
 #define ML_LCTL_SCF_MASK			0xF
 #define AZX_MLCTL_SPA				(0x1 << 16)
 #define AZX_MLCTL_CPA				(0x1 << 23)
diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index 211ca85acd8c..cfab60d88c92 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -270,6 +270,11 @@  int snd_hdac_ext_bus_link_get(struct hdac_bus *bus,
 
 		ret = snd_hdac_ext_bus_link_power_up(link);
 
+		/*
+		 * clear the register to invalidate all the output streams
+		 */
+		snd_hdac_updatew(link->ml_addr, AZX_REG_ML_LOSIDV,
+				 ML_LOSIDV_STREAM_MASK, 0);
 		/*
 		 *  wait for 521usec for codec to report status
 		 *  HDA spec section 4.3 - Codec Discovery