From patchwork Wed Oct 2 18:00:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 11171745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22FD51920 for ; Wed, 2 Oct 2019 18:02:35 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2EEA21D82 for ; Wed, 2 Oct 2019 18:02:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F2EEA21D82 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iFiw1-0005Ld-NL; Wed, 02 Oct 2019 18:01:09 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iFiw0-0005LE-52 for xen-devel@lists.xenproject.org; Wed, 02 Oct 2019 18:01:08 +0000 X-Inumbo-ID: 955a0812-e53e-11e9-971c-12813bfff9fa Received: from foss.arm.com (unknown [217.140.110.172]) by localhost (Halon) with ESMTP id 955a0812-e53e-11e9-971c-12813bfff9fa; Wed, 02 Oct 2019 18:00:56 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A23E1000; Wed, 2 Oct 2019 11:00:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9E2403F706; Wed, 2 Oct 2019 11:00:55 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Wed, 2 Oct 2019 19:00:45 +0100 Message-Id: <20191002180047.17144-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191002180047.17144-1-julien.grall@arm.com> References: <20191002180047.17144-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.13 4/6] xen/arm: cpufeature: Match register size with value size in cpus_have_const_cap X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Artem_Mygaiev@epam.com, Volodymyr Babchuk , Julien Grall , Stefano Stabellini , Julien Grall MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Clang is pickier than GCC for the register size in asm statement. It expects the register size to match the value size. The asm statement expects a 32-bit (resp. 64-bit) value on Arm32 (resp. Arm64) whereas the value is a boolean (Clang consider to be 32-bit). It would be possible to impose 32-bit register for both architecture but this require the code to use __OP32. However, it does no really improve the assembly generated. Instead, replace switch the variable to use register_t. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Use !! per Stefano's request --- xen/include/asm-arm/cpufeature.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index c2c8f3417c..4c5ff6e8ac 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -67,14 +67,14 @@ static inline bool cpus_have_cap(unsigned int num) /* System capability check for constant cap */ #define cpus_have_const_cap(num) ({ \ - bool __ret; \ + register_t __ret; \ \ asm volatile (ALTERNATIVE("mov %0, #0", \ "mov %0, #1", \ num) \ : "=r" (__ret)); \ \ - unlikely(__ret); \ + unlikely(!!__ret); \ }) static inline void cpus_set_cap(unsigned int num)