| Message ID | 20191004090114.30694-6-glaroque@baylibre.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Add support of New Amlogic temperature sensor for G12 SoCs | expand |
On Fri, Oct 4, 2019 at 2:31 PM Guillaume La Roque <glaroque@baylibre.com> wrote: > > Add missing #colling-cells field for G12A SoC > Add cooling-map for passive and hot trip point > > Tested-by: Christian Hewitt <christianshewitt@gmail.com> > Tested-by: Kevin Hilman <khilman@baylibre.com> > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> > Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 24 +++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index 733a9d46fc4b..3ab6497548ca 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -18,6 +18,7 @@ > reg = <0x0 0x0>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu1: cpu@1 { > @@ -26,6 +27,7 @@ > reg = <0x0 0x1>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu2: cpu@2 { > @@ -34,6 +36,7 @@ > reg = <0x0 0x2>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu3: cpu@3 { > @@ -42,6 +45,7 @@ > reg = <0x0 0x3>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > l2: l2-cache0 { > @@ -113,3 +117,23 @@ > &sd_emmc_a { > amlogic,dram-access-quirk; > }; > + > +&cpu_thermal { > + cooling-maps { > + map0 { > + trip = <&cpu_passive>; > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu_hot>; > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > +}; > -- > 2.17.1 >
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 733a9d46fc4b..3ab6497548ca 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -18,6 +18,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -26,6 +27,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -34,6 +36,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -42,6 +45,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; l2: l2-cache0 { @@ -113,3 +117,23 @@ &sd_emmc_a { amlogic,dram-access-quirk; }; + +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +};