[2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes
diff mbox series

Message ID 20191008161441.12721-2-ville.syrjala@linux.intel.com
State New
Headers show
Series
  • [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
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Commit Message

Ville Syrjälä Oct. 8, 2019, 4:14 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we expose VLV/CHV alpha blending only on the sprite
planes, but the primary planes can do it as well. Let's flip
it on.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 2 files changed, 57 insertions(+), 1 deletion(-)

Comments

Shankar, Uma Oct. 29, 2019, 10:01 a.m. UTC | #1
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary
>planes
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we expose VLV/CHV alpha blending only on the sprite planes, but the
>primary planes can do it as well. Let's flip it on.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h              |  1 +
> 2 files changed, 57 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1a533ccdb54f..1cdcd0ea0564 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -98,6 +98,20 @@ static const u32 i965_primary_formats[] = {
> 	DRM_FORMAT_XBGR2101010,
> };
>
>+/* Primary plane formats for vlv/chv */ static const u32
>+vlv_primary_formats[] = {
>+	DRM_FORMAT_C8,
>+	DRM_FORMAT_RGB565,
>+	DRM_FORMAT_XRGB8888,
>+	DRM_FORMAT_XBGR8888,
>+	DRM_FORMAT_ARGB8888,
>+	DRM_FORMAT_ABGR8888,
>+	DRM_FORMAT_XRGB2101010,
>+	DRM_FORMAT_XBGR2101010,
>+	DRM_FORMAT_ARGB2101010,
>+	DRM_FORMAT_ABGR2101010,
>+};
>+
> static const u64 i9xx_format_modifiers[] = {
> 	I915_FORMAT_MOD_X_TILED,
> 	DRM_FORMAT_MOD_LINEAR,
>@@ -2952,6 +2966,8 @@ static int i9xx_format_to_fourcc(int format)
> 	switch (format) {
> 	case DISPPLANE_8BPP:
> 		return DRM_FORMAT_C8;
>+	case DISPPLANE_BGRA555:
>+		return DRM_FORMAT_ARGB1555;
> 	case DISPPLANE_BGRX555:
> 		return DRM_FORMAT_XRGB1555;
> 	case DISPPLANE_BGRX565:
>@@ -2961,10 +2977,18 @@ static int i9xx_format_to_fourcc(int format)
> 		return DRM_FORMAT_XRGB8888;
> 	case DISPPLANE_RGBX888:
> 		return DRM_FORMAT_XBGR8888;
>+	case DISPPLANE_BGRA888:
>+		return DRM_FORMAT_ARGB8888;
>+	case DISPPLANE_RGBA888:
>+		return DRM_FORMAT_ABGR8888;
> 	case DISPPLANE_BGRX101010:
> 		return DRM_FORMAT_XRGB2101010;
> 	case DISPPLANE_RGBX101010:
> 		return DRM_FORMAT_XBGR2101010;
>+	case DISPPLANE_BGRA101010:
>+		return DRM_FORMAT_ARGB2101010;
>+	case DISPPLANE_RGBA101010:
>+		return DRM_FORMAT_ABGR2101010;
> 	}
> }
>
>@@ -3639,6 +3663,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> 	case DRM_FORMAT_XRGB1555:
> 		dspcntr |= DISPPLANE_BGRX555;
> 		break;
>+	case DRM_FORMAT_ARGB1555:
>+		dspcntr |= DISPPLANE_BGRA555;
>+		break;
> 	case DRM_FORMAT_RGB565:
> 		dspcntr |= DISPPLANE_BGRX565;
> 		break;
>@@ -3648,12 +3675,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> 	case DRM_FORMAT_XBGR8888:
> 		dspcntr |= DISPPLANE_RGBX888;
> 		break;
>+	case DRM_FORMAT_ARGB8888:
>+		dspcntr |= DISPPLANE_BGRA888;
>+		break;
>+	case DRM_FORMAT_ABGR8888:
>+		dspcntr |= DISPPLANE_RGBA888;
>+		break;
> 	case DRM_FORMAT_XRGB2101010:
> 		dspcntr |= DISPPLANE_BGRX101010;
> 		break;
> 	case DRM_FORMAT_XBGR2101010:
> 		dspcntr |= DISPPLANE_RGBX101010;
> 		break;
>+	case DRM_FORMAT_ARGB2101010:
>+		dspcntr |= DISPPLANE_BGRA101010;
>+		break;
>+	case DRM_FORMAT_ABGR2101010:
>+		dspcntr |= DISPPLANE_RGBA101010;
>+		break;
> 	default:
> 		MISSING_CASE(fb->format->format);
> 		return 0;
>@@ -14634,8 +14673,12 @@ static bool i965_plane_format_mod_supported(struct
>drm_plane *_plane,
> 	case DRM_FORMAT_RGB565:
> 	case DRM_FORMAT_XRGB8888:
> 	case DRM_FORMAT_XBGR8888:
>+	case DRM_FORMAT_ARGB8888:
>+	case DRM_FORMAT_ABGR8888:
> 	case DRM_FORMAT_XRGB2101010:
> 	case DRM_FORMAT_XBGR2101010:
>+	case DRM_FORMAT_ARGB2101010:
>+	case DRM_FORMAT_ABGR2101010:
> 		return modifier == DRM_FORMAT_MOD_LINEAR ||
> 			modifier == I915_FORMAT_MOD_X_TILED;
> 	default:
>@@ -14855,7 +14898,19 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> 		fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
> 	}
>
>-	if (INTEL_GEN(dev_priv) >= 4) {
>+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>+		formats = vlv_primary_formats;
>+		num_formats = ARRAY_SIZE(vlv_primary_formats);
>+		modifiers = i9xx_format_modifiers;
>+
>+		plane->max_stride = i9xx_plane_max_stride;
>+		plane->update_plane = i9xx_update_plane;
>+		plane->disable_plane = i9xx_disable_plane;
>+		plane->get_hw_state = i9xx_plane_get_hw_state;
>+		plane->check_plane = i9xx_plane_check;
>+
>+		plane_funcs = &i965_plane_funcs;

These seems to be duplicated, but since this is already refactored in later patch so 
should be ok.

Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>+	} else if (INTEL_GEN(dev_priv) >= 4) {
> 		formats = i965_primary_formats;
> 		num_formats = ARRAY_SIZE(i965_primary_formats);
> 		modifiers = i9xx_format_modifiers;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>1dc067fc57ab..8bd75eff1266 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6270,6 +6270,7 @@ enum {
> #define   DISPPLANE_RGBX101010			(0x8 << 26)
> #define   DISPPLANE_RGBA101010			(0x9 << 26)
> #define   DISPPLANE_BGRX101010			(0xa << 26)
>+#define   DISPPLANE_BGRA101010			(0xb << 26)
> #define   DISPPLANE_RGBX161616			(0xc << 26)
> #define   DISPPLANE_RGBX888			(0xe << 26)
> #define   DISPPLANE_RGBA888			(0xf << 26)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1a533ccdb54f..1cdcd0ea0564 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -98,6 +98,20 @@  static const u32 i965_primary_formats[] = {
 	DRM_FORMAT_XBGR2101010,
 };
 
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_ABGR2101010,
+};
+
 static const u64 i9xx_format_modifiers[] = {
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2952,6 +2966,8 @@  static int i9xx_format_to_fourcc(int format)
 	switch (format) {
 	case DISPPLANE_8BPP:
 		return DRM_FORMAT_C8;
+	case DISPPLANE_BGRA555:
+		return DRM_FORMAT_ARGB1555;
 	case DISPPLANE_BGRX555:
 		return DRM_FORMAT_XRGB1555;
 	case DISPPLANE_BGRX565:
@@ -2961,10 +2977,18 @@  static int i9xx_format_to_fourcc(int format)
 		return DRM_FORMAT_XRGB8888;
 	case DISPPLANE_RGBX888:
 		return DRM_FORMAT_XBGR8888;
+	case DISPPLANE_BGRA888:
+		return DRM_FORMAT_ARGB8888;
+	case DISPPLANE_RGBA888:
+		return DRM_FORMAT_ABGR8888;
 	case DISPPLANE_BGRX101010:
 		return DRM_FORMAT_XRGB2101010;
 	case DISPPLANE_RGBX101010:
 		return DRM_FORMAT_XBGR2101010;
+	case DISPPLANE_BGRA101010:
+		return DRM_FORMAT_ARGB2101010;
+	case DISPPLANE_RGBA101010:
+		return DRM_FORMAT_ABGR2101010;
 	}
 }
 
@@ -3639,6 +3663,9 @@  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_XRGB1555:
 		dspcntr |= DISPPLANE_BGRX555;
 		break;
+	case DRM_FORMAT_ARGB1555:
+		dspcntr |= DISPPLANE_BGRA555;
+		break;
 	case DRM_FORMAT_RGB565:
 		dspcntr |= DISPPLANE_BGRX565;
 		break;
@@ -3648,12 +3675,24 @@  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_XBGR8888:
 		dspcntr |= DISPPLANE_RGBX888;
 		break;
+	case DRM_FORMAT_ARGB8888:
+		dspcntr |= DISPPLANE_BGRA888;
+		break;
+	case DRM_FORMAT_ABGR8888:
+		dspcntr |= DISPPLANE_RGBA888;
+		break;
 	case DRM_FORMAT_XRGB2101010:
 		dspcntr |= DISPPLANE_BGRX101010;
 		break;
 	case DRM_FORMAT_XBGR2101010:
 		dspcntr |= DISPPLANE_RGBX101010;
 		break;
+	case DRM_FORMAT_ARGB2101010:
+		dspcntr |= DISPPLANE_BGRA101010;
+		break;
+	case DRM_FORMAT_ABGR2101010:
+		dspcntr |= DISPPLANE_RGBA101010;
+		break;
 	default:
 		MISSING_CASE(fb->format->format);
 		return 0;
@@ -14634,8 +14673,12 @@  static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_ABGR8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_ARGB2101010:
+	case DRM_FORMAT_ABGR2101010:
 		return modifier == DRM_FORMAT_MOD_LINEAR ||
 			modifier == I915_FORMAT_MOD_X_TILED;
 	default:
@@ -14855,7 +14898,19 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+		formats = vlv_primary_formats;
+		num_formats = ARRAY_SIZE(vlv_primary_formats);
+		modifiers = i9xx_format_modifiers;
+
+		plane->max_stride = i9xx_plane_max_stride;
+		plane->update_plane = i9xx_update_plane;
+		plane->disable_plane = i9xx_disable_plane;
+		plane->get_hw_state = i9xx_plane_get_hw_state;
+		plane->check_plane = i9xx_plane_check;
+
+		plane_funcs = &i965_plane_funcs;
+	} else if (INTEL_GEN(dev_priv) >= 4) {
 		formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
 		modifiers = i9xx_format_modifiers;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc067fc57ab..8bd75eff1266 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6270,6 +6270,7 @@  enum {
 #define   DISPPLANE_RGBX101010			(0x8 << 26)
 #define   DISPPLANE_RGBA101010			(0x9 << 26)
 #define   DISPPLANE_BGRX101010			(0xa << 26)
+#define   DISPPLANE_BGRA101010			(0xb << 26)
 #define   DISPPLANE_RGBX161616			(0xc << 26)
 #define   DISPPLANE_RGBX888			(0xe << 26)
 #define   DISPPLANE_RGBA888			(0xf << 26)