[3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
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Message ID 20191008161441.12721-3-ville.syrjala@linux.intel.com
State New
Headers show
Series
  • [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
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Commit Message

Ville Syrjälä Oct. 8, 2019, 4:14 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the the primary
plane. Add the require bits to expose the new formats.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h             | 14 +++++----
 2 files changed, 39 insertions(+), 8 deletions(-)

Comments

Shankar, Uma Oct. 29, 2019, 11:53 a.m. UTC | #1
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B
>sprites on CHV
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
>On VLV and CHV pipe A/C these are only supported by the the primary plane. Add the

Drop the redundant "the".
CHV indeed has this additional capability on pipe B (MPO pipe) sprites.

Overall changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>require bits to expose the new formats.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h             | 14 +++++----
> 2 files changed, 39 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 90b0e65420a5..fb36da58390a 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> 	case DRM_FORMAT_ABGR2101010:
> 		sprctl |= SP_FORMAT_RGBA1010102;
> 		break;
>+	case DRM_FORMAT_XRGB2101010:
>+		sprctl |= SP_FORMAT_BGRX1010102;
>+		break;
>+	case DRM_FORMAT_ARGB2101010:
>+		sprctl |= SP_FORMAT_BGRA1010102;
>+		break;
> 	case DRM_FORMAT_XBGR8888:
> 		sprctl |= SP_FORMAT_RGBX8888;
> 		break;
>@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
> 	DRM_FORMAT_VYUY,
> };
>
>+static const u32 chv_pipe_b_sprite_formats[] = {
>+	DRM_FORMAT_RGB565,
>+	DRM_FORMAT_ABGR8888,
>+	DRM_FORMAT_ARGB8888,
>+	DRM_FORMAT_XBGR8888,
>+	DRM_FORMAT_XRGB8888,
>+	DRM_FORMAT_XBGR2101010,
>+	DRM_FORMAT_ABGR2101010,
>+	DRM_FORMAT_XRGB2101010,
>+	DRM_FORMAT_ARGB2101010,
>+	DRM_FORMAT_YUYV,
>+	DRM_FORMAT_YVYU,
>+	DRM_FORMAT_UYVY,
>+	DRM_FORMAT_VYUY,
>+};
>+
> static const u32 skl_plane_formats[] = {
> 	DRM_FORMAT_C8,
> 	DRM_FORMAT_RGB565,
>@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> 	case DRM_FORMAT_XRGB8888:
> 	case DRM_FORMAT_XBGR2101010:
> 	case DRM_FORMAT_ABGR2101010:
>+	case DRM_FORMAT_XRGB2101010:
>+	case DRM_FORMAT_ARGB2101010:
> 	case DRM_FORMAT_YUYV:
> 	case DRM_FORMAT_YVYU:
> 	case DRM_FORMAT_UYVY:
>@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private
>*dev_priv,
> 		plane->get_hw_state = vlv_plane_get_hw_state;
> 		plane->check_plane = vlv_sprite_check;
>
>-		formats = vlv_plane_formats;
>-		num_formats = ARRAY_SIZE(vlv_plane_formats);
>+		if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
>+			formats = chv_pipe_b_sprite_formats;
>+			num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
>+		} else {
>+			formats = vlv_plane_formats;
>+			num_formats = ARRAY_SIZE(vlv_plane_formats);
>+		}
> 		modifiers = i9xx_plane_format_modifiers;
>
> 		plane_funcs = &vlv_sprite_funcs;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>8bd75eff1266..74bb5a6cbe4f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6545,12 +6545,14 @@ enum {
> #define   SP_ENABLE			(1 << 31)
> #define   SP_GAMMA_ENABLE		(1 << 30)
> #define   SP_PIXFORMAT_MASK		(0xf << 26)
>-#define   SP_FORMAT_YUV422		(0 << 26)
>-#define   SP_FORMAT_BGR565		(5 << 26)
>-#define   SP_FORMAT_BGRX8888		(6 << 26)
>-#define   SP_FORMAT_BGRA8888		(7 << 26)
>-#define   SP_FORMAT_RGBX1010102		(8 << 26)
>-#define   SP_FORMAT_RGBA1010102		(9 << 26)
>+#define   SP_FORMAT_YUV422		(0x0 << 26)
>+#define   SP_FORMAT_BGR565		(0x5 << 26)
>+#define   SP_FORMAT_BGRX8888		(0x6 << 26)
>+#define   SP_FORMAT_BGRA8888		(0x7 << 26)
>+#define   SP_FORMAT_RGBX1010102		(0x8 << 26)
>+#define   SP_FORMAT_RGBA1010102		(0x9 << 26)
>+#define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
>+#define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
> #define   SP_FORMAT_RGBX8888		(0xe << 26)
> #define   SP_FORMAT_RGBA8888		(0xf << 26)
> #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 90b0e65420a5..fb36da58390a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -861,6 +861,12 @@  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_ABGR2101010:
 		sprctl |= SP_FORMAT_RGBA1010102;
 		break;
+	case DRM_FORMAT_XRGB2101010:
+		sprctl |= SP_FORMAT_BGRX1010102;
+		break;
+	case DRM_FORMAT_ARGB2101010:
+		sprctl |= SP_FORMAT_BGRA1010102;
+		break;
 	case DRM_FORMAT_XBGR8888:
 		sprctl |= SP_FORMAT_RGBX8888;
 		break;
@@ -2017,6 +2023,22 @@  static const u32 vlv_plane_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static const u32 chv_pipe_b_sprite_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
 static const u32 skl_plane_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
@@ -2241,6 +2263,8 @@  static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_ABGR2101010:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_ARGB2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
@@ -2637,8 +2661,13 @@  intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		plane->get_hw_state = vlv_plane_get_hw_state;
 		plane->check_plane = vlv_sprite_check;
 
-		formats = vlv_plane_formats;
-		num_formats = ARRAY_SIZE(vlv_plane_formats);
+		if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
+			formats = chv_pipe_b_sprite_formats;
+			num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
+		} else {
+			formats = vlv_plane_formats;
+			num_formats = ARRAY_SIZE(vlv_plane_formats);
+		}
 		modifiers = i9xx_plane_format_modifiers;
 
 		plane_funcs = &vlv_sprite_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd75eff1266..74bb5a6cbe4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6545,12 +6545,14 @@  enum {
 #define   SP_ENABLE			(1 << 31)
 #define   SP_GAMMA_ENABLE		(1 << 30)
 #define   SP_PIXFORMAT_MASK		(0xf << 26)
-#define   SP_FORMAT_YUV422		(0 << 26)
-#define   SP_FORMAT_BGR565		(5 << 26)
-#define   SP_FORMAT_BGRX8888		(6 << 26)
-#define   SP_FORMAT_BGRA8888		(7 << 26)
-#define   SP_FORMAT_RGBX1010102		(8 << 26)
-#define   SP_FORMAT_RGBA1010102		(9 << 26)
+#define   SP_FORMAT_YUV422		(0x0 << 26)
+#define   SP_FORMAT_BGR565		(0x5 << 26)
+#define   SP_FORMAT_BGRX8888		(0x6 << 26)
+#define   SP_FORMAT_BGRA8888		(0x7 << 26)
+#define   SP_FORMAT_RGBX1010102		(0x8 << 26)
+#define   SP_FORMAT_RGBA1010102		(0x9 << 26)
+#define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
+#define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
 #define   SP_FORMAT_RGBX8888		(0xe << 26)
 #define   SP_FORMAT_RGBA8888		(0xf << 26)
 #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */