| Message ID | 20191008161441.12721-4-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites | expand |
>-----Original Message----- >From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala >Sent: Tuesday, October 8, 2019 9:45 PM >To: intel-gfx@lists.freedesktop.org >Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes > >From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >VLV/CHV sprite planes also support the C8 format. Let's expose that. Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >--- > drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 7 insertions(+) > >diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c >b/drivers/gpu/drm/i915/display/intel_sprite.c >index fb36da58390a..4cd0982dc8a2 100644 >--- a/drivers/gpu/drm/i915/display/intel_sprite.c >+++ b/drivers/gpu/drm/i915/display/intel_sprite.c >@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state >*crtc_state, > case DRM_FORMAT_VYUY: > sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; > break; >+ case DRM_FORMAT_C8: >+ sprctl |= SP_FORMAT_8BPP; >+ break; > case DRM_FORMAT_RGB565: > sprctl |= SP_FORMAT_BGR565; > break; >@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = { }; > > static const u32 vlv_plane_formats[] = { >+ DRM_FORMAT_C8, > DRM_FORMAT_RGB565, > DRM_FORMAT_ABGR8888, > DRM_FORMAT_ARGB8888, >@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = { }; > > static const u32 chv_pipe_b_sprite_formats[] = { >+ DRM_FORMAT_C8, > DRM_FORMAT_RGB565, > DRM_FORMAT_ABGR8888, > DRM_FORMAT_ARGB8888, >@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct >drm_plane *_plane, > } > > switch (format) { >+ case DRM_FORMAT_C8: > case DRM_FORMAT_RGB565: > case DRM_FORMAT_ABGR8888: > case DRM_FORMAT_ARGB8888: >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index >74bb5a6cbe4f..577468928ffa 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -6546,6 +6546,7 @@ enum { > #define SP_GAMMA_ENABLE (1 << 30) > #define SP_PIXFORMAT_MASK (0xf << 26) > #define SP_FORMAT_YUV422 (0x0 << 26) >+#define SP_FORMAT_8BPP (0x2 << 26) > #define SP_FORMAT_BGR565 (0x5 << 26) > #define SP_FORMAT_BGRX8888 (0x6 << 26) > #define SP_FORMAT_BGRA8888 (0x7 << 26) >-- >2.21.0 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index fb36da58390a..4cd0982dc8a2 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_VYUY: sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; break; + case DRM_FORMAT_C8: + sprctl |= SP_FORMAT_8BPP; + break; case DRM_FORMAT_RGB565: sprctl |= SP_FORMAT_BGR565; break; @@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = { }; static const u32 vlv_plane_formats[] = { + DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, @@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = { }; static const u32 chv_pipe_b_sprite_formats[] = { + DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, @@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, } switch (format) { + case DRM_FORMAT_C8: case DRM_FORMAT_RGB565: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_ARGB8888: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 74bb5a6cbe4f..577468928ffa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6546,6 +6546,7 @@ enum { #define SP_GAMMA_ENABLE (1 << 30) #define SP_PIXFORMAT_MASK (0xf << 26) #define SP_FORMAT_YUV422 (0x0 << 26) +#define SP_FORMAT_8BPP (0x2 << 26) #define SP_FORMAT_BGR565 (0x5 << 26) #define SP_FORMAT_BGRX8888 (0x6 << 26) #define SP_FORMAT_BGRA8888 (0x7 << 26)