From patchwork Wed Oct 9 08:33:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 11180795 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 721B314ED for ; Wed, 9 Oct 2019 08:35:24 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4B2E7206C0 for ; Wed, 9 Oct 2019 08:35:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="bVxJrnRd" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4B2E7206C0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iI7Po-0007v0-Mo; Wed, 09 Oct 2019 08:33:48 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iI7Pn-0007uv-Je for xen-devel@lists.xenproject.org; Wed, 09 Oct 2019 08:33:47 +0000 X-Inumbo-ID: 826b6364-ea6f-11e9-80e3-bc764e2007e4 Received: from esa5.hc3370-68.iphmx.com (unknown [216.71.155.168]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 826b6364-ea6f-11e9-80e3-bc764e2007e4; Wed, 09 Oct 2019 08:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1570610026; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6A1sQGAniOlPZhUjO1yap2vKJ5ys/ILjqGXAJosKfSM=; b=bVxJrnRdGwCCTJubSKmyC5hZetxMoNignK3yxjNMbPBDk7UV2g1uRxZ4 bnsAW0CGYEB6yzQHxGlAZN7VUe5RaEplyZPCRQx/WRbuDy+XdrryvwHin eXecNmFsNtWLdZ3V3E4LF+22tzFqnlOOhrr0jCqRCWTy5vWJHvi1hXixC E=; Authentication-Results: esa5.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=roger.pau@citrix.com; spf=Pass smtp.mailfrom=roger.pau@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: None (esa5.hc3370-68.iphmx.com: no sender authenticity information available from domain of roger.pau@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa5.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa5.hc3370-68.iphmx.com: domain of roger.pau@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa5.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa5.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa5.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: D1681cwg//u3uqcvvkZ5BoVUtdyIk8bnghMrwlHD2BXUGLob4dfFboo1DqDfgcNbCkhTSQFBv3 0+8SmRwM8EvhQxIahEZwu5H/dWoV4l84DmQsLMM0tYm6vH356rqzmfSFByzdKSy1hy59rQ5Tjq 4g7wySHQ2K6c9Qy8peY1j/PT5VxULtao9JbmLLGhXFA4aVpWigkSl72Ef2WhGDm5CJPubCcR+O RhPoSVOBRUDo7c7E2fd7YQzEmNYtC+d17WPw6zUDLOfqWYBdJxB4HzqvxCsYhQvwYECUhHSoYX oEw= X-SBRS: 2.7 X-MesageID: 6909076 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.67,273,1566878400"; d="scan'208";a="6909076" From: Roger Pau Monne To: Date: Wed, 9 Oct 2019 10:33:21 +0200 Message-ID: <20191009083321.1743-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v2] pci: clear {host/guest}_maskall field on assign X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Andrew Cooper , "Spassov, Stanislav" , Jan Beulich , Roger Pau Monne , Chao Gao Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The current implementation of host_maskall makes it sticky across assign and deassign calls, which means that once a guest forces Xen to set host_maskall the maskall bit is not going to be cleared until a call to PHYSDEVOP_prepare_msix is performed. Such call however shouldn't be part of the normal flow when doing PCI passthrough, and hence the flag needs to be cleared when assigning in order to prevent host_maskall being carried over from previous assignations. Note that the entry maskbit is reset when the msix capability is initialized, and the guest_maskall field is also cleared so that the hardware value matches Xen's internal state (hardware maskall = host_maskall | guest_maskall). Also note that doing the reset of host_maskall there would allow the guest to reset such field by enabling and disabling MSIX, which is not intended. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich Tested-by: Chao Gao --- Cc: Chao Gao Cc: "Spassov, Stanislav" Cc: Pasi Kärkkäinen --- Chao, Stanislav, can you please check if this patch fixes your issues? --- Changes since v1: - Also set guest_maskall. - Place the code in a helper function in x86/msi.c - Add a comment to describe the expected state. - Test that maskall is not set on hardware. --- xen/arch/x86/msi.c | 22 ++++++++++++++++++++++ xen/drivers/passthrough/pci.c | 5 +++++ xen/include/asm-x86/msi.h | 1 + 3 files changed, 28 insertions(+) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 76d4034c4f..c239a00fb1 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -1249,6 +1249,28 @@ void pci_cleanup_msi(struct pci_dev *pdev) msi_free_irqs(pdev); } +int pci_reset_msix_state(struct pci_dev *pdev) +{ + unsigned int pos = pci_find_cap_offset(pdev->seg, pdev->bus, pdev->sbdf.dev, + pdev->sbdf.fn, PCI_CAP_ID_MSIX); + + ASSERT(pos); + /* + * Xen expects the device state to be the after reset one, and hence + * host_maskall = guest_maskall = false and all entries should have the + * mask bit set. Test that the maskall bit is not set, having it set could + * signal that the device hasn't been reset properly. + */ + if ( pci_conf_read16(pdev->sbdf, msix_control_reg(pos)) & + PCI_MSIX_FLAGS_MASKALL ) + return -EBUSY; + + pdev->msix->host_maskall = false; + pdev->msix->guest_maskall = false; + + return 0; +} + int pci_msi_conf_write_intercept(struct pci_dev *pdev, unsigned int reg, unsigned int size, uint32_t *data) { diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 90ccb8370b..bdcc482d81 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -1505,7 +1505,12 @@ static int assign_device(struct domain *d, u16 seg, u8 bus, u8 devfn, u32 flag) } if ( pdev->msix ) + { + rc = pci_reset_msix_state(pdev); + if ( rc ) + goto done; msixtbl_init(d); + } pdev->fault.count = 0; diff --git a/xen/include/asm-x86/msi.h b/xen/include/asm-x86/msi.h index d0b0045d0d..6e35713ec7 100644 --- a/xen/include/asm-x86/msi.h +++ b/xen/include/asm-x86/msi.h @@ -92,6 +92,7 @@ extern int __setup_msi_irq(struct irq_desc *, struct msi_desc *, extern void teardown_msi_irq(int irq); extern int msi_free_vector(struct msi_desc *entry); extern int pci_restore_msi_state(struct pci_dev *pdev); +extern int pci_reset_msix_state(struct pci_dev *pdev); struct msi_desc { struct msi_attrib {