| Message ID | 1570619086-30088-1-git-send-email-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [v3] PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init() | expand |
Hi Shimoda-san, On Wed, Oct 9, 2019 at 1:05 PM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register > should be written to 0 before enabling PCIETCTLR.CFINIT because > the bit 0 is set to 1 on reset. To avoid unexpected behaviors from > this incorrect setting, this patch fixes it. > > Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") > Cc: <stable@vger.kernel.org> # v3.16+ > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Changes from v2: > - Change the subject. > - Fix commit log again. > - Add the register setting into the initialization, instead of speedup. > - Change commit hash/target version on Fixes and Cc stable tags. > - Add Geert-san's Reviewed-by. > https://patchwork.kernel.org/patch/11180429/ Thanks for the update! > --- a/drivers/pci/controller/pcie-rcar.c > +++ b/drivers/pci/controller/pcie-rcar.c > @@ -93,6 +93,7 @@ > #define LINK_SPEED_2_5GTS (1 << 16) > #define LINK_SPEED_5_0GTS (2 << 16) > #define MACCTLR 0x011058 > +#define MACCTLR_RESERVED BIT(0) > #define SPEED_CHANGE BIT(24) > #define SCRAMBLE_DISABLE BIT(27) > #define PMSR 0x01105c > @@ -615,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) > if (IS_ENABLED(CONFIG_PCI_MSI)) > rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); > > + rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); > + > /* Finish initialization - establish a PCI Express link */ > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); I guess the same should be added to rcar_pcie_resume_noirq(), as s2ram on R-Car Gen3 powers down the SoC? Gr{oetje,eeting}s, Geert
Hi Geert-san, > From: Geert Uytterhoeven, Sent: Wednesday, October 9, 2019 8:31 PM > > Hi Shimoda-san, > > On Wed, Oct 9, 2019 at 1:05 PM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: <snip> > > @@ -615,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) > > if (IS_ENABLED(CONFIG_PCI_MSI)) > > rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); > > > > + rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); > > + > > /* Finish initialization - establish a PCI Express link */ > > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > I guess the same should be added to rcar_pcie_resume_noirq(), > as s2ram on R-Car Gen3 powers down the SoC? Thank you for the pointed it out! You're correct. So, I'll update the patch. Best regards, Yoshihiro Shimoda > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index f6a669a..8d0798c 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -93,6 +93,7 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define MACCTLR_RESERVED BIT(0) #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -615,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); + rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); + /* Finish initialization - establish a PCI Express link */ rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register should be written to 0 before enabling PCIETCTLR.CFINIT because the bit 0 is set to 1 on reset. To avoid unexpected behaviors from this incorrect setting, this patch fixes it. Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes from v2: - Change the subject. - Fix commit log again. - Add the register setting into the initialization, instead of speedup. - Change commit hash/target version on Fixes and Cc stable tags. - Add Geert-san's Reviewed-by. https://patchwork.kernel.org/patch/11180429/ Changes from v1: - Fix commit log. - Add Sergei-san's Reviewed-by. https://patchwork.kernel.org/patch/11179279/ drivers/pci/controller/pcie-rcar.c | 3 +++ 1 file changed, 3 insertions(+)