From patchwork Thu Oct 10 00:12:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 11182429 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7DBD17D4 for ; Thu, 10 Oct 2019 00:12:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 97212206C0 for ; Thu, 10 Oct 2019 00:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732481AbfJJAMi (ORCPT ); Wed, 9 Oct 2019 20:12:38 -0400 Received: from muru.com ([72.249.23.125]:36782 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732334AbfJJAMi (ORCPT ); Wed, 9 Oct 2019 20:12:38 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 593B78162; Thu, 10 Oct 2019 00:13:11 +0000 (UTC) From: Tony Lindgren To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Merlijn Wajer , Pavel Machek , Sebastian Reichel Subject: [PATCH 7/8] ARM: OMAP2+: Allow core oswr for omap4 Date: Wed, 9 Oct 2019 17:12:23 -0700 Message-Id: <20191010001224.41826-8-tony@atomide.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191010001224.41826-1-tony@atomide.com> References: <20191010001224.41826-1-tony@atomide.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Commit f74297dd9354 ("ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared") disabled oswr (open switch retention) for per and core domains as various GPIO related issues were noticed if the bootloader had configured the bits for LOGICRETSTATE for per and core domains. With the recent gpio-omap fixes, mostly related to commit e6818d29ea15 ("gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup"), things now behave for enabling core oswr for omap4. Cc: Merlijn Wajer Cc: Pavel Machek Cc: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm44xx.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -128,18 +128,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) return 0; } - /* - * Bootloader or kexec boot may have LOGICRETSTATE cleared - * for some domains. This is the case when kexec booting from - * Android kernels that support off mode for example. - * Make sure it's set at least for core and per, otherwise - * we currently will see lost GPIO interrupts for wlcore and - * smsc911x at least if per hits retention during idle. - */ - if (!strncmp(pwrdm->name, "core", 4) - pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET); - - if (!strncmp(pwrdm->name, "l4per", 5) + if (!strncmp(pwrdm->name, "core", 4) || + !strncmp(pwrdm->name, "l4per", 5)) pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF); pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);