From patchwork Fri Oct 11 20:09:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11186341 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB569139A for ; Fri, 11 Oct 2019 20:10:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B068721D7F for ; Fri, 11 Oct 2019 20:10:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B068721D7F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3730F6EC94; Fri, 11 Oct 2019 20:10:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 04E5C6EC9D for ; Fri, 11 Oct 2019 20:10:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="188418340" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 11 Oct 2019 13:10:13 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:10:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:48 +0300 Message-Id: <20191011200949.7839-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/8] drm/i915: Move linetime wms into the crtc state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The linetime watermarks really have very little in common with the plane watermarks. It looks to be cleaner to simply track them in the crtc_state and program them from the normal modeset/fastset paths. The only dark cloud comes from the fact that the register is still supposedly single buffered. So in theory it might still need some form of two stage programming. Note that even though HSW/BDWhave two stage programming we never computed any special intermediate values for the linetime watermarks, and on SKL+ we don't even have the two stage stuff plugged in since everything else is double buffered. So let's assume it's all fine and continue doing what we've been doing. Actually on HSW/BDW the value should not even change without a full modeset since it doesn't account for pfit downscaling. Thus only fastboot might be affected. But on SKL+ the pfit scaling factor is take into consideration so the value may change during any fastset. As a bonus we'll plug this thing into the state checker/dump now. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 94 +++++++++++++- .../drm/i915/display/intel_display_types.h | 7 +- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 116 +----------------- 4 files changed, 97 insertions(+), 121 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9eab67bbf61d..3eb6f337dff0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6397,6 +6397,16 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); } +static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + I915_WRITE(WM_LINETIME(crtc->pipe), + HSW_LINETIME(crtc_state->linetime) | + HSW_IPS_LINETIME(crtc_state->linetime)); +} + static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct intel_atomic_state *state) { @@ -6465,6 +6475,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (INTEL_GEN(dev_priv) < 9) intel_disable_primary_plane(pipe_config); + hsw_set_linetime_wm(pipe_config); + if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(intel_crtc); @@ -10401,6 +10413,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, enum intel_display_power_domain power_domain; u64 power_domain_mask; bool active; + u32 tmp; intel_crtc_init_scalers(crtc, pipe_config); @@ -10464,7 +10477,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); if (INTEL_GEN(dev_priv) >= 9) { - u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); + tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) pipe_config->gamma_enable = true; @@ -10477,6 +10490,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, intel_color_get_config(pipe_config); + tmp = I915_READ(WM_LINETIME(crtc->pipe)); + pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + pipe_config->ips_linetime = + REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); WARN_ON(power_domain_mask & BIT_ULL(power_domain)); @@ -11784,6 +11803,53 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; } +static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + + if (!crtc_state->base.enable) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + adjusted_mode->crtc_clock); +} + +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + const struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->base.state); + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + + if (!crtc_state->base.enable) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + state->cdclk.logical.cdclk); +} + +static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + u16 linetime_wm; + + if (!crtc_state->base.enable) + return 0; + + linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8, + crtc_state->pixel_rate); + + /* Display WA #1135: BXT:ALL GLK:ALL */ + if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) + linetime_wm /= 2; + + return linetime_wm; +} + static int intel_crtc_atomic_check(struct drm_crtc *_crtc, struct drm_crtc_state *_crtc_state) { @@ -11861,6 +11927,13 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc, if (HAS_IPS(dev_priv)) crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state); + if (INTEL_GEN(dev_priv) >= 9) { + crtc_state->linetime = skl_linetime_wm(crtc_state); + } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + crtc_state->linetime = hsw_linetime_wm(crtc_state); + crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state); + } + return ret; } @@ -12154,6 +12227,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config->pixel_rate); + DRM_DEBUG_KMS("linetime: %d, ips linetime: %d\n", + pipe_config->linetime, pipe_config->ips_linetime); + if (INTEL_GEN(dev_priv) >= 9) DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", crtc->num_scalers, @@ -12836,10 +12912,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(gamma_enable); PIPE_CONF_CHECK_BOOL(csc_enable); + PIPE_CONF_CHECK_I(linetime); + PIPE_CONF_CHECK_I(ips_linetime); + bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); if (bp_gamma) PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma); - } PIPE_CONF_CHECK_BOOL(double_wide); @@ -13711,6 +13789,18 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, ironlake_pfit_disable(old_crtc_state); } + /* + * The register is supposedly single buffered so perhaps + * not 100% correct to do this here. But SKL+ calculate + * this based on the adjust pixel rate so pfit changes do + * affect it and so it must be updated for fastsets. + * HSW/BDW only really need this here for fastboot, after + * that the value should not change without a full modeset. + */ + if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + hsw_set_linetime_wm(new_crtc_state); + if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 841952332c7e..9b606e507778 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -631,8 +631,6 @@ struct intel_crtc_scaler_state { struct intel_pipe_wm { struct intel_wm_level wm[5]; - u16 linetime; - u16 ips_linetime; bool fbc_wm_enabled; bool pipe_enabled; bool sprites_enabled; @@ -648,7 +646,6 @@ struct skl_plane_wm { struct skl_pipe_wm { struct skl_plane_wm planes[I915_MAX_PLANES]; - u32 linetime; }; enum vlv_wm_level { @@ -990,6 +987,10 @@ struct intel_crtc_state { } dsc_params; struct drm_dsc_config dp_dsc_cfg; + /* HSW+ linetime watermarks */ + u16 linetime; + u16 ips_linetime; + /* Forward Error correction State */ bool fec_enable; }; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c46b339064c0..eba9055c4405 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -842,7 +842,6 @@ struct ilk_wm_values { u32 wm_pipe[3]; u32 wm_lp[3]; u32 wm_lp_spr[3]; - u32 wm_linetime[3]; bool enable_fbc_wm; enum intel_ddb_partitioning partitioning; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f6893b771078..390d1f8d45ba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2763,34 +2763,6 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, result->enable = true; } -static u32 -hsw_linetime_wm(const struct intel_crtc_state *crtc_state) -{ - const struct drm_display_mode *adjusted_mode = - &crtc_state->base.adjusted_mode; - - if (!crtc_state->base.active) - return 0; - - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - adjusted_mode->crtc_clock); -} - -static u32 -hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) -{ - const struct intel_atomic_state *state = - to_intel_atomic_state(crtc_state->base.state); - const struct drm_display_mode *adjusted_mode = - &crtc_state->base.adjusted_mode; - - if (!crtc_state->base.active) - return 0; - - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - state->cdclk.logical.cdclk); -} - static void intel_read_wm_latency(struct drm_i915_private *dev_priv, u16 wm[8]) { @@ -3128,11 +3100,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state) ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state, pristate, sprstate, curstate, &pipe_wm->wm[0]); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - pipe_wm->linetime = hsw_linetime_wm(crtc_state); - pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state); - } - if (!ilk_validate_pipe_wm(dev_priv, pipe_wm)) return -EINVAL; @@ -3384,10 +3351,6 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, if (WARN_ON(!r->enable)) continue; - results->wm_linetime[pipe] = - HSW_LINETIME(pipe_wm->linetime) | - HSW_IPS_LINETIME(pipe_wm->ips_linetime); - results->wm_pipe[pipe] = (r->pri_val << WM0_PIPE_PLANE_SHIFT) | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | @@ -3426,7 +3389,6 @@ ilk_find_best_result(struct drm_i915_private *dev_priv, /* dirty bits used to track which watermarks need changes */ #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) -#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) #define WM_DIRTY_FBC (1 << 24) @@ -3441,12 +3403,6 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, int wm_lp; for_each_pipe(dev_priv, pipe) { - if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { - dirty |= WM_DIRTY_LINETIME(pipe); - /* Must disable LP1+ watermarks too */ - dirty |= WM_DIRTY_LP_ALL; - } - if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { dirty |= WM_DIRTY_PIPE(pipe); /* Must disable LP1+ watermarks too */ @@ -3538,13 +3494,6 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, if (dirty & WM_DIRTY_PIPE(PIPE_C)) I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); - if (dirty & WM_DIRTY_LINETIME(PIPE_A)) - I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]); - if (dirty & WM_DIRTY_LINETIME(PIPE_B)) - I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]); - if (dirty & WM_DIRTY_LINETIME(PIPE_C)) - I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]); - if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { val = I915_READ(WM_MISC); @@ -4884,24 +4833,6 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, } } -static u32 -skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state) -{ - struct drm_atomic_state *state = crtc_state->base.state; - struct drm_i915_private *dev_priv = to_i915(state->dev); - uint_fixed_16_16_t linetime_us; - u32 linetime_wm; - - linetime_us = intel_get_linetime_us(crtc_state); - linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us)); - - /* Display WA #1135: BXT:ALL GLK:ALL */ - if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) - linetime_wm /= 2; - - return linetime_wm; -} - static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, const struct skl_wm_params *wp, struct skl_plane_wm *wm) @@ -5089,8 +5020,6 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state) return ret; } - pipe_wm->linetime = skl_compute_linetime_wm(crtc_state); - return 0; } @@ -5215,7 +5144,7 @@ static bool skl_pipe_wm_equals(struct intel_crtc *crtc, return false; } - return wm1->linetime == wm2->linetime; + return true; } static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, @@ -5591,38 +5520,6 @@ skl_compute_wm(struct intel_atomic_state *state) return 0; } -static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, - struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; - enum pipe pipe = crtc->pipe; - - if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0) - return; - - I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime)); -} - -static void skl_initial_wm(struct intel_atomic_state *state, - struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct skl_ddb_values *results = &state->wm_results; - - if ((results->dirty_pipes & BIT(crtc->pipe)) == 0) - return; - - mutex_lock(&dev_priv->wm.wm_mutex); - - if (crtc_state->base.active_changed) - skl_atomic_update_crtc_wm(state, crtc_state); - - mutex_unlock(&dev_priv->wm.wm_mutex); -} - static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, struct intel_wm_config *config) { @@ -5743,9 +5640,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, if (!crtc->active) return; - - val = I915_READ(WM_LINETIME(pipe)); - out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val); } void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) @@ -5786,8 +5680,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) }; hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe)); memset(active, 0, sizeof(*active)); @@ -5806,10 +5698,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; - active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, - hw->wm_linetime[pipe]); - active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK, - hw->wm_linetime[pipe]); } else { int level, max_level = ilk_wm_max_level(dev_priv); @@ -8993,8 +8881,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv) /* For FIFO watermark updates */ if (INTEL_GEN(dev_priv) >= 9) { skl_setup_wm_latency(dev_priv); - dev_priv->display.initial_watermarks = skl_initial_wm; - dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; dev_priv->display.compute_global_watermarks = skl_compute_wm; } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv);