From patchwork Mon Oct 14 12:38:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11188649 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC835139A for ; Mon, 14 Oct 2019 12:38:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6D2D21744 for ; Mon, 14 Oct 2019 12:38:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6D2D21744 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBF936E25F; Mon, 14 Oct 2019 12:38:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0EED76E29B for ; Mon, 14 Oct 2019 12:38:37 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id n14so19506109wrw.9 for ; Mon, 14 Oct 2019 05:38:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZUMaf0SNyeTXqJDQ2zj2y54gRfa0la6e9vYK/qX/aYM=; b=bEN1zxdwAxQ3vAca3mi2EIv8jqAKgkBKoVh5umTmzc0AqYgWlwOv7CaD5YSRaV6e0h JrBqfFhi2l1m8YjOx7RKhlym+YESZAAOxlzDFp8oEpaMQXT+TF0D1JH0vYLXyoVcHsWM Hf6RLGKqMm0aBpGtdrs9FHdV0gWkI4Hy/+Inla4wSOij6NhyfMrweQAHia86dAJ/HqGK NVNgYbM+1MZltDA2zfibNv3JfK6oCfbLSrR9/DKIJMMOd7Znc3ATGmkFe6MkAx9Qc1zj AcGAzlxm9TKkbFVwLntmnK7fpEQ3S1KufgTEj8Zhx0H7RlBQhojpz5aKClbjSaMAXz1u CO2Q== X-Gm-Message-State: APjAAAWz24U18glxuJ9FQKvS55N1qtTklzozVN3ZNWV1UFljfd4STMVs F50mQoI6JIhJI7cL8UgCdexM1NUJKechHQ== X-Google-Smtp-Source: APXvYqzJNRPaaQMtvLEpbINL9YKBHIeyCgYQe7WPDcGPn9WtfZyiiCXRhhBXXx0P44Rp/tMTr2rkZQ== X-Received: by 2002:adf:fd0a:: with SMTP id e10mr24001667wrr.55.1571056714934; Mon, 14 Oct 2019 05:38:34 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id 3sm19171203wmo.22.2019.10.14.05.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2019 05:38:34 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH v2 5/7] drm/meson: viu: add AFBC modules routing functions Date: Mon, 14 Oct 2019 14:38:24 +0200 Message-Id: <20191014123826.27629-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191014123826.27629-1-narmstrong@baylibre.com> References: <20191014123826.27629-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZUMaf0SNyeTXqJDQ2zj2y54gRfa0la6e9vYK/qX/aYM=; b=ydNvvSOIkPhQ/svDJzvckOn8NGmrpiGQKRN4sWqCiyG8VvMcy9AdVdAhx5IrlQlY8Z qYJkB241N2Rf+6QtFjqR8t5enA8Mhs/m3fWs3+SNC9OxjJG7MLcx/M8RD8d9n45T37yB nUcsIyD84PSuNj/yrOMhSmZ1KoJEns+tv3h461zXd3SVG2JDmGQU1XOCJpsriijIlzBZ UkI2N2pLp+0HqUgifVnOyzQ8KTUAKvqEb/4tCfznijqPvGHrtSdTClR1lGUxK73zwujo 8kF4tV4M7Vzil0vf/95G+kH9gf2u2/2veLGCjRglDFUeXfr3YCATeW9OZM+miK0u9Ikm 5VnA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , khilman@baylibre.com, linux-amlogic@lists.infradead.org, ayan.halder@arm.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic G12A AFBC Decoder pixel input need to be routed diferently than the Amlogic GXM AFBC decoder, this adds support for routing the VIU OSD1 pixel source to the AFBC "Mali Unpack" module. This "Mali Unpack" module is also configured with a static RGBA mapping for now until we support more pixel formats. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_viu.c | 76 +++++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_viu.h | 4 ++ 2 files changed, 80 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index 68cf2c2eca5f..07713588063e 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -7,6 +7,9 @@ */ #include +#include + +#include #include "meson_drv.h" #include "meson_viu.h" @@ -335,6 +338,79 @@ void meson_viu_osd1_reset(struct meson_drm *priv) meson_viu_load_matrix(priv); } +#define OSD1_MALI_ORDER_ABGR \ + (FIELD_PREP(VIU_OSD1_MALI_AFBCD_A_REORDER, \ + VIU_OSD1_MALI_REORDER_A) | \ + FIELD_PREP(VIU_OSD1_MALI_AFBCD_B_REORDER, \ + VIU_OSD1_MALI_REORDER_B) | \ + FIELD_PREP(VIU_OSD1_MALI_AFBCD_G_REORDER, \ + VIU_OSD1_MALI_REORDER_G) | \ + FIELD_PREP(VIU_OSD1_MALI_AFBCD_R_REORDER, \ + VIU_OSD1_MALI_REORDER_R)) + +#define OSD1_MALI_ORDER_ARGB \ + (FIELD_PREP(VIU_OSD1_MALI_AFBCD_A_REORDER, \ + VIU_OSD1_MALI_REORDER_A) | \ + FIELD_PREP(VIU_OSD1_MALI_AFBCD_B_REORDER, \ + VIU_OSD1_MALI_REORDER_R) | \ + FIELD_PREP(VIU_OSD1_MALI_AFBCD_G_REORDER, \ + VIU_OSD1_MALI_REORDER_G) | \ + FIELD_PREP(VIU_OSD1_MALI_AFBCD_R_REORDER, \ + VIU_OSD1_MALI_REORDER_B)) + +void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv) +{ + u32 afbc_order = OSD1_MALI_ORDER_ARGB; + + /* Enable Mali AFBC Unpack */ + writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN, + VIU_OSD1_MALI_UNPACK_EN, + priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); + + switch (priv->afbcd.format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + afbc_order = OSD1_MALI_ORDER_ABGR; + break; + } + + /* Setup RGBA Reordering */ + writel_bits_relaxed(VIU_OSD1_MALI_AFBCD_A_REORDER | + VIU_OSD1_MALI_AFBCD_B_REORDER | + VIU_OSD1_MALI_AFBCD_G_REORDER | + VIU_OSD1_MALI_AFBCD_R_REORDER, + afbc_order, + priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); + + /* Select AFBCD path for OSD1 */ + writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, + OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, + priv->io_base + _REG(OSD_PATH_MISC_CTRL)); +} + +void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv) +{ + /* Disable AFBCD path for OSD1 */ + writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, 0, + priv->io_base + _REG(OSD_PATH_MISC_CTRL)); + + /* Disable AFBCD unpack */ + writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN, 0, + priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); +} + +void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv) +{ + writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x90), + priv->io_base + _REG(VIU_MISC_CTRL1)); +} + +void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv) +{ + writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x00), + priv->io_base + _REG(VIU_MISC_CTRL1)); +} + static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length) { uint32_t val = (((length & 0x80) % 24) / 12); diff --git a/drivers/gpu/drm/meson/meson_viu.h b/drivers/gpu/drm/meson/meson_viu.h index e297772d967f..e4a2f24d7c38 100644 --- a/drivers/gpu/drm/meson/meson_viu.h +++ b/drivers/gpu/drm/meson/meson_viu.h @@ -63,6 +63,10 @@ #define OSD_PENDING_STAT_CLEAN BIT(1) void meson_viu_osd1_reset(struct meson_drm *priv); +void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv); +void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv); +void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv); +void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv); void meson_viu_init(struct meson_drm *priv); #endif /* __MESON_VIU_H */