| Message ID | 1571108362-25962-1-git-send-email-pankaj.dubey@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | [v3] PCI: dwc: Add support to add GEN3 related equalization quirks | expand |
On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote: > From: Anvesh Salveru <anvesh.s@samsung.com> > > In some platforms, PCIe PHY may have issues which will prevent linkup > to happen in GEN3 or higher speed. In case equalization fails, link will > fallback to GEN1. > > DesignWare controller gives flexibility to disable GEN3 equalization > completely or only phase 2 and 3 of equalization. > > This patch enables the DesignWare driver to disable the PCIe GEN3 > equalization by enabling one of the following quirks: > - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases > - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3 > > Platform drivers can set these quirks via "quirk" variable of "dw_pcie" > struct. Please submit this together with the changes to the dwc frontend driver that actually wants to set these quirks.
> -----Original Message----- > From: Christoph Hellwig <hch@infradead.org> > Sent: Tuesday, October 15, 2019 1:46 PM > To: Pankaj Dubey <pankaj.dubey@samsung.com> > Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelgaas@google.com; andrew.murray@arm.com; lorenzo.pieralisi@arm.com; > gustavo.pimentel@synopsys.com; jingoohan1@gmail.com; vidyas@nvidia.com; > Anvesh Salveru <anvesh.s@samsung.com> > Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related equalization > quirks > > On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote: > > From: Anvesh Salveru <anvesh.s@samsung.com> > > > > In some platforms, PCIe PHY may have issues which will prevent linkup > > to happen in GEN3 or higher speed. In case equalization fails, link > > will fallback to GEN1. > > > > DesignWare controller gives flexibility to disable GEN3 equalization > > completely or only phase 2 and 3 of equalization. > > > > This patch enables the DesignWare driver to disable the PCIe GEN3 > > equalization by enabling one of the following quirks: > > - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases > > - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3 > > > > Platform drivers can set these quirks via "quirk" variable of "dw_pcie" > > struct. > > Please submit this together with the changes to the dwc frontend driver that > actually wants to set these quirks. Is this something mandatory? As we discussed during first patch-set here [1] with Andrew, we have need of this patch (along with some other stuffs, which will be sent soon), to clean up our internal driver and make it ready for upstream. As of today we have some internal restrictions where we can't make it to upstream along with this patch. [1]: https://patchwork.ozlabs.org/patch/1160310/#2258262
On Tue, Oct 15, 2019 at 02:28:00PM +0530, Pankaj Dubey wrote: > Is this something mandatory? > > As we discussed during first patch-set here [1] with Andrew, we have need of > this patch (along with some other stuffs, which will be sent soon), to clean > up our internal driver and make it ready for upstream. As of today we have > some internal restrictions where we can't make it to upstream along with > this patch. We don't add code to the kernel without actual users.
> -----Original Message----- > From: 'Christoph Hellwig' <hch@infradead.org> > Sent: Tuesday, October 15, 2019 2:36 PM > To: Pankaj Dubey <pankaj.dubey@samsung.com> > Cc: 'Christoph Hellwig' <hch@infradead.org>; linux-pci@vger.kernel.org; linux- > kernel@vger.kernel.org; bhelgaas@google.com; andrew.murray@arm.com; > lorenzo.pieralisi@arm.com; gustavo.pimentel@synopsys.com; > jingoohan1@gmail.com; vidyas@nvidia.com; 'Anvesh Salveru' > <anvesh.s@samsung.com> > Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related equalization > quirks > > On Tue, Oct 15, 2019 at 02:28:00PM +0530, Pankaj Dubey wrote: > > Is this something mandatory? > > > > As we discussed during first patch-set here [1] with Andrew, we have > > need of this patch (along with some other stuffs, which will be sent > > soon), to clean up our internal driver and make it ready for upstream. > > As of today we have some internal restrictions where we can't make it > > to upstream along with this patch. > > We don't add code to the kernel without actual users. OK, but do we think the current driver has only code which is being used by some user? At least I can see current driver has some features which is not being used by any current driver. I will leave this call up-to the maintainers. IMO, This being an DWC H/W IP feature, for me it makes sense to have it in DWC controller driver as long as it does not break any existing functionality, irrespective of actual user is present or not.
On Tue, Oct 15, 2019 at 08:47:32PM +0530, Pankaj Dubey wrote: > OK, but do we think the current driver has only code which is being used by > some user? That is at least the intent of how we do kernel development. > At least I can see current driver has some features which is not being used > by any current driver. Please send patches to remove them.
On 10/16/19, 2:52 AM, 'Christoph Hellwig' wrote: > > On Tue, Oct 15, 2019 at 08:47:32PM +0530, Pankaj Dubey wrote: > > OK, but do we think the current driver has only code which is being used by > > some user? > > That is at least the intent of how we do kernel development. Agreed! > > > At least I can see current driver has some features which is not being used > > by any current driver. > > Please send patches to remove them. Agreed! Mainline kernel should not include features that have not been used. Thank you. Best regards, Jingoo Han
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 820488d..e247d6d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -556,4 +556,16 @@ void dw_pcie_setup(struct dw_pcie *pci) PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + + if (pci->quirk & DWC_EQUALIZATION_DISABLE) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val |= PORT_LOGIC_GEN3_EQ_DISABLE; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } + + if (pci->quirk & DWC_EQ_PHASE_2_3_DISABLE) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5a18e94..7d3fe6f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -29,6 +29,10 @@ #define LINK_WAIT_MAX_IATU_RETRIES 5 #define LINK_WAIT_IATU 9 +/* Parameters for GEN3 related quirks */ +#define DWC_EQUALIZATION_DISABLE BIT(1) +#define DWC_EQ_PHASE_2_3_DISABLE BIT(2) + /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_MODE_MASK GENMASK(21, 16) @@ -60,6 +64,10 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) +#define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) #define PCIE_ATU_REGION_OUTBOUND 0 @@ -253,6 +261,7 @@ struct dw_pcie { struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; unsigned int version; + unsigned int quirk; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)