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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id a9sm7412463oie.7.2019.10.16.13.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 13:07:28 -0700 (PDT) From: Rob Herring To: Andrew Murray , Bjorn Helgaas , Lorenzo Pieralisi Subject: [PATCH v2 21/25] PCI: v3-semi: Use inbound resources for setup Date: Wed, 16 Oct 2019 15:06:43 -0500 Message-Id: <20191016200647.32050-22-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191016200647.32050-1-robh@kernel.org> References: <20191016200647.32050-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191016_130730_552711_CA64500D X-CRM114-Status: GOOD ( 14.97 ) X-Spam-Score: 0.6 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.167.196 listed in wl.mailspike.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [209.85.167.196 listed in list.dnswl.org] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (robherring2[at]gmail.com) 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (robherring2[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different 0.1 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and EnvelopeFrom freemail headers are different X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , Karthikeyan Mitran , linux-pci@vger.kernel.org, Shawn Lin , Thomas Petazzoni , Toan Le , Will Deacon , Ryder Lee , Michal Simek , linux-rockchip@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Linus Walleij , Ray Jui , Hou Zhiqiang , Simon Horman , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org, Scott Branden , Jingoo Han , rfi@lists.rocketboards.org, linux-renesas-soc@vger.kernel.org, Tom Joseph , Srinath Mannam , Gustavo Pimentel , Ley Foon Tan Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Now that the helpers provide the inbound resources in the host bridge 'dma_ranges' resource list, convert the v3-semi host bridge to use the resource list to setup the inbound addresses. Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Reviewed-by: Andrew Murray Reviewed-by: Linus Walleij Signed-off-by: Rob Herring --- drivers/pci/controller/pci-v3-semi.c | 38 ++++++++++++---------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pci-v3-semi.c b/drivers/pci/controller/pci-v3-semi.c index 2209c7671115..bd05221f5a22 100644 --- a/drivers/pci/controller/pci-v3-semi.c +++ b/drivers/pci/controller/pci-v3-semi.c @@ -598,28 +598,30 @@ static int v3_pci_setup_resource(struct v3_pci *v3, } static int v3_get_dma_range_config(struct v3_pci *v3, - struct of_pci_range *range, + struct resource_entry *entry, u32 *pci_base, u32 *pci_map) { struct device *dev = v3->dev; - u64 cpu_end = range->cpu_addr + range->size - 1; - u64 pci_end = range->pci_addr + range->size - 1; + u64 cpu_addr = entry->res->start; + u64 cpu_end = entry->res->end; + u64 pci_end = cpu_end - entry->offset; + u64 pci_addr = entry->res->start - entry->offset; u32 val; - if (range->pci_addr & ~V3_PCI_BASE_M_ADR_BASE) { + if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) { dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n"); return -EINVAL; } - val = ((u32)range->pci_addr) & V3_PCI_BASE_M_ADR_BASE; + val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE; *pci_base = val; - if (range->cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) { + if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) { dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n"); return -EINVAL; } - val = ((u32)range->cpu_addr) & V3_PCI_MAP_M_MAP_ADR; + val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR; - switch (range->size) { + switch (resource_size(entry->res)) { case SZ_1M: val |= V3_LB_BASE_ADR_SIZE_1MB; break; @@ -667,8 +669,8 @@ static int v3_get_dma_range_config(struct v3_pci *v3, dev_dbg(dev, "DMA MEM CPU: 0x%016llx -> 0x%016llx => " "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n", - range->cpu_addr, cpu_end, - range->pci_addr, pci_end, + cpu_addr, cpu_end, + pci_addr, pci_end, *pci_base, *pci_map); return 0; @@ -677,24 +679,16 @@ static int v3_get_dma_range_config(struct v3_pci *v3, static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3, struct device_node *np) { - struct of_pci_range range; - struct of_pci_range_parser parser; + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3); struct device *dev = v3->dev; + struct resource_entry *entry; int i = 0; - if (of_pci_dma_range_parser_init(&parser, np)) { - dev_err(dev, "missing dma-ranges property\n"); - return -EINVAL; - } - - /* - * Get the dma-ranges from the device tree - */ - for_each_of_pci_range(&parser, &range) { + resource_list_for_each_entry(entry, &bridge->dma_ranges) { int ret; u32 pci_base, pci_map; - ret = v3_get_dma_range_config(v3, &range, &pci_base, &pci_map); + ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map); if (ret) return ret;